yosys

History

Clifford Wolf 7f0548c16f Update examples/cmos/counter.ys to use "synth" command Signed-off-by: Clifford Wolf <clifford@clifford.at>		2018-05-30 14:17:36 +02:00
..
.gitignore	Cleanups and improvements in examples/cmos/	2016-03-11 11:30:01 +01:00
README	Cleanups and improvements in examples/cmos/	2016-03-11 11:30:01 +01:00
cmos_cells.lib	Added examples/ top-level directory	2015-10-13 15:41:20 +02:00
cmos_cells.sp	Added examples/ top-level directory	2015-10-13 15:41:20 +02:00
cmos_cells.v	Added examples/ top-level directory	2015-10-13 15:41:20 +02:00
cmos_cells_digital.sp	Added digital (xspice) example code to examples/cmos/	2016-03-02 12:07:57 +01:00
counter.v	Added examples/ top-level directory	2015-10-13 15:41:20 +02:00
counter.ys	Update examples/cmos/counter.ys to use "synth" command	2018-05-30 14:17:36 +02:00
counter_digital.ys	Completed ngspice digital example with verilog tb	2016-03-05 08:34:05 +01:00
counter_tb.gtkw	Cleanups and improvements in examples/cmos/	2016-03-11 11:30:01 +01:00
counter_tb.v	Squelch trailing whitespace	2017-04-12 15:11:09 +02:00
testbench.sh	Cleanups and improvements in examples/cmos/	2016-03-11 11:30:01 +01:00
testbench.sp	Added digital (xspice) example code to examples/cmos/	2016-03-02 12:07:57 +01:00
testbench_digital.sh	Squelch trailing whitespace	2017-04-12 15:11:09 +02:00
testbench_digital.sp	Completed ngspice digital example with verilog tb	2016-03-05 08:34:05 +01:00

README

In this directory contains an example for generating a spice output using two
different spice modes, normal analog transient simulation and event-driven
digital simulation as supported by ngspice xspice sub-module.

Each test bench can be run separately by either running:

- testbench.sh, to start analog simulation or
- testbench_digital.sh for mixed-signal digital simulation.

The later case also includes pure verilog simulation using the iverilog
and gtkwave for comparison.