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19 Commits
a5925cb837 ... 377f26e1f1

Author SHA1 Message Date
George Rennie 377f26e1f1
Merge 583eb1addb into 56b80bdd22 2024-11-20 13:36:12 +01:00
Emil J 56b80bdd22
Merge pull request #4448 from georgerennie/shiftadd_gating 
peepopt shiftadd: Only match for sufficiently small constant widths
 2024-11-20 13:34:09 +01:00
Emil J da8c8b4fd0
Merge pull request #4701 from georgerennie/george/pyosys_noreturn_attrs 
pyosys generator: ignore attributes
 2024-11-20 13:33:33 +01:00
Emil J cc17d5bb70
Merge pull request #4612 from georgerennie/george/opt_demorgan_zero_width 
opt_demorgan: skip zero width cells
 2024-11-20 13:33:16 +01:00
Emil J 18459b4b09
Merge pull request #4614 from georgerennie/george/opt_reduce_cell_width 
opt_reduce: keep at least one input to $reduce_or/and cells
 2024-11-20 13:33:04 +01:00
Emil J 88abc4c20f
Merge pull request #4755 from pepijndevos/cells_xtra 
Gowin: add GW2A and GW5A cells
 2024-11-20 13:32:30 +01:00
Martin Povišer 7ebe451f9a
Merge pull request #4714 from georgerennie/george/proc_dff_bug_multiple_sigs 
proc_dff: fix early return bug
 2024-11-20 13:26:32 +01:00
Martin Povišer 1184418cc8
Merge pull request #4739 from hzeller/feature-20241113-stdlib-for-abort 
Include stdlib.h for `abort()`
 2024-11-20 10:19:31 +01:00
Pepijn de Vos b8329df1d0 add GW2A and GW5A cells 2024-11-17 20:25:11 +01:00
George Rennie 583eb1addb pyosys: dereference cpp objects when constructing a tuple 
* This fixes a bug where when converting a tuple from python to c++,
  get_cpp_obj() was called (returning a pointer) without dereferencing
  the pointer to get the underlying object
 2024-11-15 15:18:18 +01:00
Henner Zeller a750c94c38 Include stdlib.h for `abort()` 2024-11-13 13:05:01 -08:00
George Rennie c23e64a236 tests/proc: add proc_dff bug 4712 as testcase 2024-11-07 00:10:17 +01:00
George Rennie 626dbbe1e0 proc_dff: fix early return bug 
* early return caused proc_dff to stop considering rules after seeing
  one async rule - this is because continue should have been used to
  continue to procecssing the next rule instead of returning from the
  function
 2024-11-07 00:06:03 +01:00
George Rennie de728c9824 pyosys generator: ignore attributes 
* this allows log_error, log_file_error and log_cmd_error which are all
  marked [[noreturn]] to be supported
 2024-11-04 14:08:57 +01:00
George Rennie 0572f8806f opt_reduce: add test for constant $reduce_and/or not being zero width 2024-09-25 16:28:41 +01:00
George Rennie 023f029dcf opt_reduce: keep at least one input to $reduce_or/and cells 2024-09-25 16:21:19 +01:00
George Rennie e105cae4a9 opt_demorgan: add test for zero width cell 2024-09-25 16:10:16 +01:00
George Rennie 58af70624f opt_demorgan: skip zero width cells 2024-09-24 14:24:59 +01:00
George Rennie 41aaaa153e peepopt shiftadd: Only match for sufficiently small constant widths 
This addresses issue #4445
 2024-06-12 14:38:12 +01:00
12 changed files with 4500 additions and 118 deletions
Show Stats Expand all files Collapse all files

2
libs/ezsat/demo_cmp.cc
View File

@ -19,6 +19,7 @@
#include "ezminisat.h"
#include <assert.h>
#include <stdlib.h>
#define INIT_X 123456789
#define INIT_Y 362436069
@ -143,4 +144,3 @@ int main()
}
return 0;
}

2
libs/ezsat/demo_vec.cc
View File

@ -19,6 +19,7 @@
#include "ezminisat.h"
#include <assert.h>
#include <stdlib.h>
#define INIT_X 123456789
#define INIT_Y 362436069
@ -109,4 +110,3 @@ int main()
return 0;
}

9
misc/py_wrap_generator.py
View File

@ -515,11 +515,11 @@ class TupleTranslator(PythonDictTranslator):
if types[0].name.split(" ")[-1] in primitive_types:
text += varname + "___tmp_0, "
else:
text += varname + "___tmp_0.get_cpp_obj(), "
text += "*" + varname + "___tmp_0.get_cpp_obj(), "
if types[1].name.split(" ")[-1] in primitive_types:
text += varname + "___tmp_1);"
else:
text += varname + "___tmp_1.get_cpp_obj());"
text += "*" + varname + "___tmp_1.get_cpp_obj());"
return text
#Generate c++ code to translate to a boost::python::tuple
@ -1273,6 +1273,11 @@ class WFunction:
func.duplicate = False
func.namespace = namespace
str_def = str_def.replace("operator ","operator")
# remove attributes from the start
if str.startswith(str_def, "[[") and "]]" in str_def:
str_def = str_def[str_def.find("]]")+2:]
if str.startswith(str_def, "static "):
func.is_static = True
str_def = str_def[7:]

4
passes/opt/opt_demorgan.cc
View File

@ -39,6 +39,10 @@ void demorgan_worker(
return;
auto insig = sigmap(cell->getPort(ID::A));
if (GetSize(insig) < 1)
return;
log("Inspecting %s cell %s (%d inputs)\n", log_id(cell->type), log_id(cell->name), GetSize(insig));
int num_inverted = 0;
for(int i=0; i<GetSize(insig); i++)

3
passes/opt/opt_reduce.cc
View File

@ -89,6 +89,9 @@ struct OptReduceWorker
RTLIL::SigSpec new_sig_a(new_sig_a_bits);
new_sig_a.sort_and_unify();
if (GetSize(new_sig_a) == 0)
new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1;
if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) {
log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
did_something = true;

5
passes/pmgen/peepopt_shiftadd.pmg
View File

@ -53,6 +53,11 @@ match add
select port(add, constport).is_fully_const()
define <IdString> varport (constport == \A ? \B : \A)
// only optimize for constants up to a fixed width. this prevents cases
// with a blowup in internal term size and prevents larger constants being
// casted to int incorrectly
select (GetSize(port(add, constport)) <= 24)
// if a value of var is able to wrap the output, the transformation might give wrong results
// an addition/substraction can at most flip one more bit than the largest operand (the carry bit)
// as long as the output can show this bit, no wrap should occur (assuming all signed-ness make sense)

4
passes/proc/proc_dff.cc
View File

@ -262,7 +262,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
{
log_warning("Complex async reset for dff `%s'.\n", log_signal(sig));
gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, async_rules, proc);
return;
continue;
}
// If there is a reset condition in the async rules, use it
@ -277,7 +277,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
sync_edge->type == RTLIL::SyncType::STp,
sync_level && sync_level->type == RTLIL::SyncType::ST1,
sync_edge->signal, sync_level->signal, proc);
return;
continue;
}
gen_dff(mod, insig, rstval.as_const(), sig_q,

2
techlibs/gowin/cells_xtra.py
View File

@ -65,6 +65,8 @@ if __name__ == '__main__':
dirs = [
os.path.join(args.gowin_dir, 'IDE/simlib/gw1n/'),
os.path.join(args.gowin_dir, 'IDE/simlib/gw2a/'),
os.path.join(args.gowin_dir, 'IDE/simlib/gw5a/'),
]
with open('cells_xtra.v', 'w') as fout:

4527
techlibs/gowin/cells_xtra.v
View File

File diff suppressed because it is too large Load Diff

15
tests/opt/bug4610.ys Normal file
View File

@ -0,0 +1,15 @@
read_ilang <<EOT
autoidx 1
module \top
wire output 1 \Y
cell $reduce_or $reduce_or$rtl.v:29$20
parameter \A_SIGNED 0
parameter \A_WIDTH 0
parameter \Y_WIDTH 1
connect \A { }
connect \Y \Y
end
end
EOT
equiv_opt -assert opt_demorgan

14
tests/opt/opt_reduce_andor.ys Normal file
View File

@ -0,0 +1,14 @@
# Check that opt_reduce doesn't produce zero width $reduce_or/$reduce_and,
read_verilog <<EOT
module reduce_const(output wire o, output wire a);
wire [3:0] zero = 4'b0000;
wire [3:0] ones = 4'b1111;
assign o = |zero;
assign a = &ones;
endmodule
EOT
equiv_opt -assert opt_reduce
design -load postopt
select -assert-none r:A_WIDTH=0

31
tests/proc/bug4712.ys Normal file
View File

@ -0,0 +1,31 @@
read_rtlil <<EOT
autoidx 1
module \top
wire input 1 \clk
wire input 2 \rst
wire input 3 \a_r
wire input 4 \a_n
wire input 5 \b_n
wire \a
wire \b
process $proc
sync high \rst
update \a \a_r
update \b \b
sync posedge \clk
update \a \a_n
update \b \b_n
end
end
EOT
proc_dff
proc_clean
# Processes should have been converted to one aldff and one dff
select -assert-none p:*
select -assert-count 1 t:$aldff
select -assert-count 1 t:$dff