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opt_reduce: keep at least one input to $reduce_or/and cells

This commit is contained in:
George Rennie 2024-09-25 16:20:29 +01:00
parent 8e1e2b9a39
commit 023f029dcf
1 changed files with 3 additions and 0 deletions
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3
passes/opt/opt_reduce.cc
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@ -89,6 +89,9 @@ struct OptReduceWorker
RTLIL::SigSpec new_sig_a(new_sig_a_bits);
new_sig_a.sort_and_unify();
if (GetSize(new_sig_a) == 0)
new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1;
if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) {
log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
did_something = true;