Commit Graph

14435 Commits

Author SHA1 Message Date
github-actions[bot] 47bdb3e32f Bump version 2024-04-11 00:16:34 +00:00
Emil J c5912f4f95
Merge pull request #4313 from widlarizer/emil/fix-opt-demorgan-warning
opt_demorgan: fix extra args warning
2024-04-10 12:49:14 +02:00
Martin Povišer b00abe4a26 Extend `log` command with `-push`, `-pop`, `-header` options 2024-04-10 11:49:20 +02:00
Miodrag Milanovic e2cfcbcf25 fix .gitignore 2024-04-10 10:12:05 +02:00
Miodrag Milanovic e01e942f81 Next dev cycle 2024-04-10 08:21:35 +02:00
Miodrag Milanovic a1bb0255d6 Release version 0.40 2024-04-10 08:17:27 +02:00
N. Engelhardt 3d5e23e585
Merge pull request #4302 from YosysHQ/vhdl_2019
Verific support for VHDL 2019
2024-04-09 18:25:05 +02:00
N. Engelhardt 18afa36acd
Merge pull request #4273 from YosysHQ/vhdl_params
verific: Improve import VHDL constants
2024-04-09 18:01:41 +02:00
github-actions[bot] bc14999287 Bump version 2024-04-09 00:16:14 +00:00
Jannis Harder eb6c9395bf
Merge pull request #4312 from jix/break-cyclic-includes
kernel: Avoid including files outside include guards
2024-04-08 20:49:52 +02:00
Martin Povišer dc746080f5
Merge pull request #4298 from povik/kogge-stone
techmap: Add a Kogge-Stone option for `$lcu` mapping
2024-04-08 16:46:06 +02:00
Martin Povišer 5f4d13ee3f techmap: Note down iteration in Kogge-Stone 2024-04-08 16:45:40 +02:00
N. Engelhardt 8e8885e1cc
Merge pull request #4323 from YosysHQ/tests_update
Tests update for latest more strict iverilog
2024-04-08 15:10:59 +02:00
Miodrag Milanovic 4ac10040ce Enable SV for localparam use by Efinix cell_sim 2024-04-08 12:45:43 +02:00
Miodrag Milanovic 91e41d8c80 Move parameters to module declaration 2024-04-08 12:44:37 +02:00
KrystalDelusion 32bbca8586
Merge pull request #4316 from widlarizer/emil/document-macc
docs: Document $macc
2024-04-08 21:24:25 +12:00
Martin Povišer 47931f9050
Merge pull request #4295 from gadfort/add-ports-stat
add port statistics to stat command
2024-04-08 11:12:02 +02:00
Emil J. Tywoniak 43ef916f86 Restructure rst 2024-04-05 14:01:25 +02:00
Emil J. Tywoniak 9510293a94 fixup 2024-04-04 18:16:58 +02:00
github-actions[bot] 22c5ab90d1 Bump version 2024-04-04 00:16:37 +00:00
Emil J. Tywoniak a580a7c82c docs: Document $macc 2024-04-03 20:37:54 +02:00
Catherine d9a4a42389 write_verilog: don't `assign` to a `reg`.
Fixes #2035.
2024-04-03 13:06:45 +02:00
Emil J. Tywoniak 4bb3b099d2 opt_demorgan: fix extra args warning 2024-04-03 10:02:53 +02:00
github-actions[bot] 040605b047 Bump version 2024-04-03 00:15:49 +00:00
Jannis Harder d8687e87b1 kernel: Avoid including files outside include guards
This adjusts the way the headers kernel/{yosys,rtlil,register,log}.h
include each other to avoid the need of including headers outside of
include guards as well as avoiding the inclusion of rtlil.h in the
middle of yosys.h with rtlil.h depending on the prefix of yosys.h, and
the suffix of yosys.h depending on rtlil.h.

To do this I moved some of the declaration in yosys.h into a new header
yosys_common.h. I'm not sure if that is strictly necessary.

Including any of these files still results in the declarations of all
these headers being included, so this shouldn't be a breaking change for
any passes or external plugins.

My main motivation for this is that ccls's (clang based language server)
include guard handling gets confused by the previous way the includes
were done. It often ends up treating the include guard as a generic
disabled preprocessor conditional, breaking navigation and highlighting
for the core RTLIL data structures.

Additionally I think avoiding cyclic includes in the middle of header
files that depend on includes being outside of include guards will also
be less confusing for developers reading the code, not only for tools
like ccls.
2024-04-02 16:53:56 +02:00
Catherine cb07710162 write_verilog: only warn on processes with sync rules.
Processes without sync rules correspond to simple decision trees that
directly correspond to `always @*` or `always_comb` blocks in Verilog,
and do not need a warning.

This removes the need to suppress warnings during the RTLIL-to-Verilog
conversion performed by Amaranth.
2024-04-02 14:48:44 +01:00
Catherine 94170388a9 fmt: if enabled, group padding zeroes.
Before this commit, the combination of `_` and `0` format characters
would produce a result like `000000001010_1010`.
After this commit, it would be `0000_0000_1010_1010`.

This has a slight quirk where a format like `{:020_b}` results in
the output `0_0000_0000_1010_1010`, which is one character longer than
requested. Python has the same behavior, and it's not clear what would
be strictly speaking correct, so Python behavior is implemented.
2024-04-02 12:13:22 +02:00
Catherine 27cb4c52b4 fmt: allow padding characters other than `'0'` and `' '`.
When converted to Verilog, padding characters are replaced with one of
these two. Otherwise padding is performed with exactly that character.
2024-04-02 12:13:22 +02:00
Catherine ddf7b46955 fmt,cxxrtl: fix printing of non-decimal signed numbers.
Also fix interaction of `NUMERIC` justification with `show_base`.
2024-04-02 12:13:22 +02:00
Catherine 00c5b60dfd fmt,cxxrtl: add option to group digits in numbers.
The option is serialized to RTLIL as `_` (to match Python's option with
the same symbol), and sets the `group` flag. This flag inserts an `_`
symbol between each group of 3 digits (for decimal) or four digits (for
binary, hex, and octal).
2024-04-02 12:13:22 +02:00
Catherine 7b94599162 fmt,cxxrtl: add option to print numeric base (`0x`, etc).
The option is serialized to RTLIL as `#` (to match Python's and Rust's
option with the same symbol), and sets the `show_base` flag. Because
the flag is called `show_base` and not e.g. `alternate_format` (which
is what Python and Rust call it), in addition to the prefixes `0x`,
`0X`, `0o`, `0b`, the RTLIL option also prints the `0d` prefix.
2024-04-02 12:13:22 +02:00
Catherine bf5a960668 fmt,cxxrtl: add `UNICHAR` format type.
This format type is used to print an Unicode character (code point) as
its UTF-8 serialization. To this end, two UTF-8 decoders (one for fmt,
one for cxxrtl) are added for rendering. When converted to a Verilog
format specifier, `UNICHAR` degrades to `%c` with the low 7 bits of
the code point, which has equivalent behavior for inputs not exceeding
ASCII. (SystemVerilog leaves source and display encodings completely
undefined.)
2024-04-02 12:13:22 +02:00
Catherine 1780e2eb1e fmt,cxxrtl: add support for `NUMERIC` justification.
Before this commit, the existing alignments were `LEFT` and `RIGHT`,
which added the `padding` character to the right and left just before
finishing formatting. However, if `padding == '0'` and the alignment is
to the right, then the padding character (digit zero) was added after
the sign, if one is present.

After this commit, the special case for `padding == '0'` is removed,
and the new justification `NUMERIC` adds the padding character like
the justification `RIGHT`, except after the sign, if one is present.
(Space, for the `SPACE_MINUS` sign mode, counts as the sign.)
2024-04-02 12:13:22 +02:00
Catherine 6d6b138607 fmt,cxxrtl: support `{,PLUS_,SPACE_}MINUS` integer formats.
The first two were already supported with the `plus` boolean flag.
The third one is a new specifier, which is allocated the ` ` character.
In addition, `MINUS` is now allocated the `-` character, but old format
where there is no `+`, `-`, or `-` in the respective position is also
accepted for compatibility.
2024-04-02 12:13:22 +02:00
Catherine 8388846e3a fmt,cxxrtl: add support for uppercase hex format.
This is necessary for translating Python format strings in Amaranth.
2024-04-02 12:13:22 +02:00
Catherine a5441bc00c fmt: `FmtPart::{STRING→LITERAL},{CHARACTER→STRING}`.
Before this commit, the `STRING` variant inserted a literal string;
the `CHARACTER` variant inserted a string. This commit renames them
to `LITERAL` and `STRING` respectively.
2024-04-02 12:13:22 +02:00
Martin Povišer 0210509dea
Merge pull request #4309 from widlarizer/emil/fix-code-style-link
docs: Update linux kernel coding style link
2024-04-02 11:29:36 +02:00
Emil J. Tywoniak 73cacd543c docs: Update linux kernel coding style link 2024-04-02 11:23:56 +02:00
github-actions[bot] b9d3bffda5 Bump version 2024-03-31 00:18:11 +00:00
Merry d07a55a852 cxxrtl: Fix sdivmod
x = x.neg(); results in the subsequent x.is_neg() always being false.
Ditto for the dividend.is_neg() != divisor.is_neg() test.
2024-03-30 07:56:11 +00:00
Miodrag Milanovic f536de0e0e Verific support for VHDL 2019 2024-03-28 13:21:55 +01:00
Martin Povišer bc087f91ed techmap: Fix using overwritten results in Kogge-Stone 2024-03-27 18:32:25 +01:00
Martin Povišer c49d6e7874 techmap: Add Kogge-Stone test 2024-03-27 11:08:26 +01:00
Martin Povišer 4570d064e5 techmap: Split out Kogge-Stone into a separate file 2024-03-27 11:07:24 +01:00
github-actions[bot] 0a854cf4ce Bump version 2024-03-26 00:15:18 +00:00
N. Engelhardt c98cdc2a42
Merge pull request #4184 from povik/check-loop-edges
Use cell edges data in `check`, improve messages
2024-03-25 16:19:35 +01:00
Miodrag Milanović c9d9b9ec2c
Merge pull request #4270 from YosysHQ/krys/config-none
Change default CONFIG to none
2024-03-25 16:13:32 +01:00
N. Engelhardt 6248d5901b
Merge pull request #4297 from chenrui333/fix-master-branch-refs
chore: fix master branch refs
2024-03-25 16:01:33 +01:00
Martin Povišer c38201e15d techmap: Add a Kogge-Stone option for `$lcu` mapping 2024-03-25 14:56:17 +01:00
Rui Chen b57a803f60
chore: fix master branch refs
Signed-off-by: Rui Chen <rui@chenrui.dev>
2024-03-24 00:41:54 -04:00