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309 Commits

Author SHA1 Message Date
Eddie Hung b66904e9cd Revert "Merge branch 'eddie/kernel_makeblackbox' into eddie/abc9_auto_dff" 
This reverts commit e08497c7c9d8a6f7a3eccddf2149c45d9ecff207, reversing
changes made to e366fd55122236a21c6daee6765724add840a1f9.
 2020-05-14 10:33:56 -07:00
Eddie Hung 039c3a5982 kernel: Module::makeblackbox() to clear connections + delete wires last 2020-05-14 10:33:56 -07:00
Eddie Hung 86ab7d3a6e kernel: Cell::getParam() to throw exception again if not found 
As it did before #1945
 2020-04-22 16:25:23 -07:00
Marcelina Kościelnicka b4d76309e1 Use default parameter value in getParam 
Fixes #1822.
 2020-04-21 19:09:00 +02:00
Marcelina Kościelnicka 06a344efcb ilang, ast: Store parameter order and default value information. 
Fixes #1819, #1820.
 2020-04-21 19:09:00 +02:00
whitequark b6f624b56b rtlil: add AttrObject::has_attribute. 2020-04-16 21:49:49 +00:00
whitequark ff7a1a1568 rtlil: add AttrObject::{get,set}_string_attribute. 
And make {get,set}_src_attribute use those functions.
 2020-04-16 21:45:29 +00:00
Eddie Hung aa552cefa3
Merge pull request #1927 from YosysHQ/eddie/design_remove_assert 
kernel: Design::remove(RTLIL::Module *) to check refcount_modules_
 2020-04-16 08:06:12 -07:00
Eddie Hung 635b2b8939 kernel: Design::remove(RTLIL::Module *) to check refcount_modules_ 2020-04-14 09:31:06 -07:00
Eddie Hung 9547d8c13e kernel: Module::makeblackbox() to clear connections too 2020-04-13 20:37:22 -07:00
Eddie Hung 371af7da38
Merge pull request #1858 from YosysHQ/eddie/fix1856 
kernel: include "kernel/constids.inc"
 2020-04-09 14:23:47 -07:00
Eddie Hung 60ffc21e64 kernel: include "kernel/constids.inc" instead of "constids.inc" 2020-04-09 09:14:03 -07:00
Marcelina Kościelnicka 516857f3ba [NFCI] Deduplicate builtin FF cell types list 
A few passes included the same list of FF cell types.  Make it a global
const instead.

The zinit pass also seems to include a list like that, but given that
it seems to be completely broken at the time (see #1568 discussion),
I'm going to pretend I didn't see that.
 2020-04-09 18:05:06 +02:00
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Eddie Hung 164dd0f6b2 kernel: Use constids.inc for global/constant IdStrings 2020-04-02 07:14:08 -07:00
Eddie Hung 37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup 
kernel: speedup by using more pass-by-const-ref
 2020-04-02 07:13:33 -07:00
Eddie Hung 348e892314 kernel: pass-by-value into Design::scratchpad_set_string() too 2020-03-27 12:21:09 -07:00
Rupert Swarbrick 044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend 
This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
 2020-03-27 16:08:26 +00:00
Eddie Hung f97b90e40b kernel: Cell::set{Port,Param}() to pass by value, but use std::move 
Otherwise cell->setPort(ID::A, cell->getPort(ID::B)) could be invalid
 2020-03-26 14:33:06 -07:00
Eddie Hung 940640ac44 kernel: SigSpec copies to not trigger pack() 2020-03-18 11:51:00 -07:00
Eddie Hung 4555b5b819 kernel: more pass by const ref, more speedups 2020-03-18 11:21:53 -07:00
Eddie Hung 8b12e97153 kernel: speedup 2020-03-18 08:48:36 -07:00
Eddie Hung bc51e609cb kernel: fix DeleteWireWorker 2020-03-17 10:22:16 -07:00
Eddie Hung 432a09af80 kernel: SigSpec use more const& + overloads to prevent implicit SigSpec 2020-03-13 08:17:39 -07:00
Eddie Hung b567f03c26 kernel: optimise Module::remove(const pool<RTLIL::Wire*>() 2020-03-12 16:00:34 -07:00
Alberto Gonzalez f0afd65035
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes. 2020-02-23 07:22:26 +00:00
Eddie Hung b523ecf2f4 specify: system timing checks to accept min:typ:max triple 2020-02-13 12:42:15 -08:00
Eddie Hung a63e2508fc Add RTLIL::constpad, init by yosys_setup(); use for abc9 2020-01-08 10:52:08 -08:00
Clifford Wolf 3edb2e708b Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2020-01-02 18:58:45 +01:00
whitequark e97e33d00d kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr. 
Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.

Also fix the Verilog frontend to never emit such constructs.
 2019-12-04 11:59:36 +00:00
Eddie Hung 6bf7114bbd Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again 2019-10-04 16:45:36 -07:00
Eddie Hung d963e8c2c6 Fix typo 2019-09-30 15:18:40 -07:00
Henner Zeller 8c2b4f0a50 Avoid work in replace() if rules empty. 
This speeds up processing when number of bits are large but there
is actually nothing to replace. Adresses part of #1382.

Signed-off-by: Henner Zeller <h.zeller@acm.org>
 2019-09-29 00:17:40 -07:00
Eddie Hung 52355f5185 Use more ID::{A,B,Y,blackbox,whitebox} 2019-08-15 14:50:10 -07:00
Clifford Wolf b25cf36856 Add YOSYS_NO_IDS_REFCNT configuration macro 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-11 12:23:16 +02:00
Clifford Wolf 390bf459fb Use ID() in kernel/*, add simple ID:: hack (to be improved upon later) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-11 11:39:46 +02:00
Clifford Wolf 8222c5735e More improvements and cleanups in IdString subsystem 
- better use of "inline" keyword
- deprecate "sticky" IDs feature
- improve handling of empty ID
- add move constructor

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-11 11:39:46 +02:00
Eddie Hung 7164996921 RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
Eddie Hung 48d0f99406 stoi -> atoi 2019-08-07 11:09:17 -07:00
Eddie Hung 234fcf1724 Fix typos 2019-08-06 19:07:45 -07:00
Eddie Hung c11ad24fd7 Use std::stoi instead of atoi(<str>.c_str()) 2019-08-06 16:45:48 -07:00
Eddie Hung e38f40af5b Use IdString::begins_with() 2019-08-06 16:42:25 -07:00
Eddie Hung 3486235338 Make liberal use of IdString.in() 2019-08-06 16:18:18 -07:00
Clifford Wolf 023086bd46 Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 04:47:55 +02:00
whitequark df6576edc8 In RTLIL::Module::check(), check process invariants. 2019-06-19 05:22:13 +00:00
Clifford Wolf 287de4b848 Add rewrite_sigspecs2, Improve remove() wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-15 16:01:00 +02:00
Matthew Daiter 6e629d2895 Minor optimization to get_attribute_bool 2019-05-07 22:04:28 -05:00
Eddie Hung d9c4644e88 Merge remote-tracking branch 'origin/master' into clifford/specify 2019-05-03 15:05:57 -07:00
Clifford Wolf 9268cd1613 Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 15:19:10 +02:00
Clifford Wolf 64925b4e8f Improve $specrule interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 22:57:10 +02:00