a5fdf3f881
gowin: Change BYTE ENABLE handling.
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When inferring we allow writing to all bytes for now.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-01-27 17:19:49 +10:00
ae991abf2e
gowin: fix the BRAM mapping.
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The primitives used have been corrected and changes have been made to the set of signals.
The empirically established need to set the OCEx signal to 1 when using READ_MODE=0 is reflected.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-01-19 15:26:37 +10:00
f19c6b4415
Enable bram for Gowin
2023-12-03 10:17:28 +01:00
309558767d
gowin: fix typo
2023-11-14 22:37:29 +00:00
7ae4041e20
ice40, ecp5, gowin: enable ABC9 by default
2023-11-13 15:28:13 +00:00
294844137b
gowin: fix abc9 attributes and specify blocks
2023-10-04 00:16:10 +01:00
7aab324e85
Merge pull request #3737 from yrabbit/all-primitives-script
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gowin: Add all the primitives.
2023-05-09 11:13:51 +02:00
30f1d10948
gowin: Fix X output of $alu techmap
2023-05-01 17:56:41 +02:00
a1dd794ff8
gowin: Add all the primitives.
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Use selected data (names, ports and parameters) from vendor file for
GW1N series primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-04-22 17:10:53 +10:00
f9a6c0fcbd
gowin: Add serialization/deserialization primitives
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Primitives are added to convert parallel signals to serial and vice versa.
IDES4, IDES8, IDES10, IDES16, IVIDEO, OSER4, OSER8, OSER10, OSER16, OVIDEO.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-04-12 09:59:57 +01:00
bb28e48136
Merge pull request #3663 from uis246/master
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gowin: Add new types of oscillator
2023-02-28 06:56:01 +01:00
ea6f562d49
gowin: Add new types of oscillator
2023-02-06 21:34:32 +00:00
dbc8b77222
gowin: Add support for emulated differential output
2023-01-29 20:48:43 -08:00
d6a1e022e1
gowin: add a new type of PLL - PLLVR
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This primitive is used in the GW1NS-4, GW1NS-4C, GW1NSR-4, GW1NSR-4C and
GW1NSER-4C chips.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-01-11 11:41:29 +10:00
de07eb11c1
Apicula now supports lutram
2022-07-03 12:45:03 +02:00
71dfbf33b2
Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.
2022-06-02 23:16:12 +02:00
e4d811561c
gowin: Use `memory_libmap` pass.
2022-05-18 17:32:56 +02:00
30bc0d26ea
gowin: Add oscillator primitives
2022-03-28 13:33:24 +02:00
19b7633aca
gowin: add support for Double Data Rate primitives
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-03-14 23:14:21 +01:00
22d9bbb308
gowin: Remove unnecessary attributes
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-02-24 05:38:33 +01:00
9b3cd4f0d8
gowin: Add support for true differential output
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2022-02-24 05:38:33 +01:00
3a62fa0c97
gowin: Add remaining block RAM blackboxes.
2022-02-12 11:48:57 +01:00
f61f2a4078
gowin: Fix LUT RAM inference, add more models.
2022-02-09 09:04:34 +01:00
15b0d717ed
iopadmap: Add native support for negative-polarity output enable.
2021-11-09 15:40:16 +01:00
4bf8deacbb
synth_gowin: move splitnets to after iopadmap ( #2435 )
2021-11-07 18:00:18 +01:00
a3eec687e0
Remove noalu from synth_gowin json output as Apicula now supports it
2021-11-07 03:04:21 +01:00
0c7461fe5e
gowin: widelut support ( #3042 )
2021-11-06 16:09:30 +01:00
c2d358484f
Gowin: deal with active-low tristate ( #2971 )
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* deal with active-low tristate
* remove empty port
* update sim models
* add expected lut1 to tests
2021-08-20 21:21:06 +02:00
0ada13cbe2
Use HTTPS for website links, gatecat email
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git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g ;
2021-06-09 12:16:56 +02:00
72787f52fc
Fixing old e-mail addresses and deadnames
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s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
cae905f551
Blackbox all whiteboxes after synthesis
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This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 21:07:20 +00:00
f155826a70
add -noalu and -json option for apicula
2020-11-30 11:43:12 +01:00
5b9a975eba
synth_gowin: Add rPLL blackbox
2020-11-11 17:06:54 +01:00
9a4f420b4b
Replace opt_rmdff with opt_dff.
2020-08-07 13:21:03 +02:00
c73ebeb90e
gowin: Use dfflegalize.
2020-07-06 12:27:46 +02:00
7f45cab27a
synth_gowin: ABC9 support
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This adds ABC9 support for synth_gowin; drastically improving
synthesis quality.
2020-07-05 22:07:17 +02:00
90b89e5ebc
Merge pull request #2232 from YosysHQ/mwk/gowin-sim-init
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gowin: Fix INIT values in sim library.
2020-07-05 12:02:31 +02:00
9beed4d771
gowin: Fix INIT values in sim library.
2020-07-05 03:03:48 +02:00
01772dec8c
gowin: replace determine_init with setundef
2020-07-04 23:26:56 +02:00
88e7f90663
Update dff2dffe, dff2dffs, zinit to new FF types.
2020-06-23 18:24:53 +02:00
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
aee439360b
Add force_downto and force_upto wire attributes.
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Fixes #2058 .
2020-05-19 01:42:40 +02:00
26cda3c247
gowin,ecp5: remove generated files in `make clean`.
2020-04-24 23:26:39 +00:00
38a0c30d65
Get rid of dffsr2dff.
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This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part. Thus, it never
actually does anything and can be safely removed.
2020-04-15 16:22:37 +02:00
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
87883f6d88
Removing cells_sim.v from bram techmap pass
2020-02-06 14:38:29 -06:00
0b0148399c
synth_*: call 'opt -fast' after 'techmap'
2020-02-05 18:39:01 -08:00
34d2fbd2f9
Add opt_lut_ins pass. ( #1673 )
2020-02-03 14:57:17 +01:00
f8d5920a7e
Merge pull request #1604 from whitequark/unify-ram-naming
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Harmonize BRAM/LUTRAM descriptions across all of Yosys
2020-01-02 21:06:17 +00:00
550310e264
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
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This commit:
* renames all remaining instances of "DRAM" (which is ambiguous)
to "LUTRAM" (which is not), finishing the work started in
the commit 698ab9be;
* renames memory rule files to brams.txt/lutrams.txt;
* adds/renames script labels map_bram/map_lutram;
* extracts where necessary script labels map_ffram and map_gates;
* adds where necessary options -nobram/-nolutram.
The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.
Per architecture:
* anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
:map_lutram, :map_ffram, :map_gates
* ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
* efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
:map_gates
* gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
rename -nodram→-nolutram (-nodram still recognized), rename
:bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
2020-01-01 12:30:00 +00:00
YRabbit
Pepijn de Vos
Lofty
Miodrag Milanović
Ralf Fuest
uis
martell
Marcelina Kościelnicka
Tim Pambor
Claire Xenia Wolf
gatecat
Konrad Beckmann
whitequark
Eddie Hung
Diego H