Yosys Bot
dfc43c38f8
Bump version
2020-09-29 00:10:05 +00:00
Miodrag Milanović
08eb0821c9
Merge pull request #2386 from btut/fix/pyinstallpath
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Fixed python installation path
2020-09-28 12:54:38 +02:00
Benedikt Tutzer
4892ec853b
Use CXXFLAGS to enable pyosys specific code before generating wrappers
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The .pyh files were generated without the CXXFLAGS. This meant that code
marked by the WITH_PYTHON flag was excluded. This is fixed by adding the
flag in the rule for .pyh files.
2020-09-25 12:57:46 +02:00
Benedikt Tutzer
9266d20afc
Fixed python installation path
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The path where python expects it's libraries seems to change from
operating system to operating system, but can be querried from the site
package.
2020-09-25 11:21:16 +02:00
Yosys Bot
cd8b2ed4e6
Bump version
2020-09-24 00:10:06 +00:00
Yosys Bot
8fbb517118
Bump version
2020-09-22 00:10:15 +00:00
Yosys Bot
c6ff947f6b
Bump version
2020-09-19 00:10:08 +00:00
Yosys Bot
7affef7c17
Bump version
2020-09-18 00:10:08 +00:00
Yosys Bot
859e52af59
Bump version
2020-09-11 00:10:06 +00:00
Yosys Bot
474cd02eb5
Bump version
2020-09-04 00:10:06 +00:00
Yosys Bot
d963bdb484
Bump version
2020-09-03 00:10:06 +00:00
Yosys Bot
463869bf4f
Bump version
2020-09-02 00:10:07 +00:00
Yosys Bot
244af8b8b7
Bump version
2020-09-01 00:10:06 +00:00
Yosys Bot
3030c2b46c
Bump version
2020-08-30 00:10:07 +00:00
Yosys Bot
f752023556
Bump version
2020-08-29 00:10:06 +00:00
Yosys Bot
c75d8c7439
Bump version
2020-08-28 00:10:07 +00:00
whitequark
a0177569ac
Merge pull request #2357 from whitequark/cxxflags-MP
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Add -MP to CXXFLAGS
2020-08-27 11:40:57 +00:00
whitequark
702f7c0253
Merge pull request #2358 from whitequark/rename-ilang-to-rtlil
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Replace "ILANG" with "RTLIL" everywhere
2020-08-27 11:24:06 +00:00
Yosys Bot
925c0f2594
Bump version
2020-08-27 00:10:06 +00:00
whitequark
00e7dec7f5
Replace "ILANG" with "RTLIL" everywhere.
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The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.
Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
2020-08-26 17:29:32 +00:00
whitequark
deb19e1574
Add -MP to CXXFLAGS.
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This avoids an issue where deleting or moving headers breaks the next
incremental build until the outdated *.d files are deleted.
2020-08-26 16:56:10 +00:00
Yosys Bot
12132b6850
Bump version
2020-08-23 00:10:08 +00:00
Yosys Bot
dc20d9e842
Bump version
2020-08-21 00:10:06 +00:00
Yosys Bot
23719ad46d
Bump version
2020-08-20 00:10:07 +00:00
Yosys Bot
93d663be62
Bump version
2020-08-19 00:10:09 +00:00
Yosys Bot
3cb3978ff4
Bump version
2020-08-14 00:10:13 +00:00
Yosys Bot
f61d62a7bc
Bump version
2020-08-13 00:10:08 +00:00
Yosys Bot
04f6158bf2
Bump version
2020-08-10 09:30:51 +00:00
Claire Wolf
c39ebe6ae0
Bump YOSYS_VER
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-31 20:57:41 +02:00
Marcelina Kościelnicka
dafe04d559
Add utility module for representing flip-flops.
2020-07-23 23:39:46 +02:00
Marcelina Kościelnicka
022af4f0ca
Add utility module for dealing with init attributes.
2020-07-23 20:49:48 +02:00
Marcelina Kościelnicka
85a1bb17ed
satgen: Move importCell out of the header.
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This function has no hope of ever getting inlined anyway, and it speeds
up yosys compile time by 7%.
2020-07-19 00:17:02 +02:00
Lucas Castro
68babb2ae4
Fix issue #2251 ( #2252 )
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* Fix #2251 - YosysJS ReferenceError: _memset is not defined.
Add '_memset' in emcc EXPORTED_FUNCTIONS in Makefile.
2020-07-09 18:50:26 +02:00
Dan Ravensloft
7d5828a706
Add option to use ccache when building
2020-07-04 19:59:39 +01:00
whitequark
778332384a
Update ABC.
2020-06-22 14:18:07 +00:00
whitequark
a0466e1a96
cxxrtl: add missing installs of include files.
2020-06-08 12:55:11 +00:00
whitequark
2384a59e2a
Merge pull request #2051 from Xiretza/makefile-cd-warning
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Suppress warning during initial clone of ABC repo
2020-05-28 10:00:49 +00:00
Xiretza
204e8b6fc6
Suppress warning during initial clone of ABC repo
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9dedac50
introduced this harmless but disconcerting warning, which was emitted
when abc/ did not yet exist and was about to be cloned:
/bin/sh: line 0: cd: abc: No such file or directory
2020-05-14 11:18:35 +02:00
Eddie Hung
b11cf67a81
Setup tests/verilog properly
2020-05-11 10:31:02 -07:00
N. Engelhardt
c9befa769f
Remove yosys libdir from LDFLAGS (and fix a typo)
2020-05-07 19:28:18 +02:00
Eddie Hung
8eb98b12c7
Makefile: git fetch all commits from $(ABCURL) repo
2020-05-06 16:23:46 -07:00
whitequark
ff7a8d0e1e
Update ABC to include WASI support fixes.
2020-05-02 00:18:33 +00:00
whitequark
b36060cc20
Fix WASI builds with abc enabled.
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This PR works around #2011 .
2020-05-01 23:57:35 +00:00
whitequark
bbde241942
Merge pull request #2001 from whitequark/wasi
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Add WASI platform support
2020-05-01 21:28:20 +00:00
Claire Wolf
667f38fe53
Merge pull request #1997 from whitequark/document-ootb
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Explain how to do out-of-tree builds in README
2020-05-01 15:35:33 +02:00
whitequark
b43c282e4e
Add WASI platform support.
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This includes the following significant changes:
* Patching ezsat and minisat to disable resource limiting code
on WASM/WASI, since the POSIX functions they use are unavailable.
* Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
does not support spawning subprocesses (i.e. Emscripten or WASI).
This definition hides the definition of `run_command()`.
* Adding a new Makefile flag, DISABLE_SPAWN, present in the same
condition. This flag disables all passes that require spawning
subprocesses for their function.
2020-04-30 18:56:25 +00:00
Eddie Hung
a3fa9fd6e9
abc: use YosysHQ/abc instead of upstream berkeley-abc/abc
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Enabling modifications
2020-04-27 12:03:40 -07:00
whitequark
f1087b2552
Fix out-of-tree builds configured as `SMALL := 1`.
2020-04-24 23:27:43 +00:00
whitequark
2ee028dcf1
Merge pull request #1900 from Xiretza/suppress-makefile-echo
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Suppress output of Makefile.conf when printing source versions
2020-04-16 13:28:34 +00:00
Dan Ravensloft
2e37e62e6b
synth_intel_alm: alternative synthesis for Intel FPGAs
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By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.
This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2020-04-15 11:40:41 +02:00