Clifford Wolf
76f20492a4
Merge pull request #1162 from whitequark/rtlil-case-attrs
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Allow attributes on individual switch cases in RTLIL
2019-07-09 18:48:38 +01:00
Clifford Wolf
17e0cc010c
Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wire
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Throw runtime exception when trying to convert inexistend C++ object to Python
2019-07-09 18:48:23 +01:00
Clifford Wolf
fecd3aa2b1
Merge pull request #1147 from YosysHQ/clifford/fix1144
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Improve specify dummy parser
2019-07-09 18:47:08 +01:00
Clifford Wolf
d105e2f03f
Merge pull request #1154 from whitequark/manual-sync-always
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manual: explain the purpose of `sync always`
2019-07-09 18:46:58 +01:00
David Shah
4b49c0201e
Merge pull request #1153 from YosysHQ/dave/fix_multi_mux
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memory_dff: Fix checking of feedback mux input when more than one mux
2019-07-09 18:46:39 +01:00
Clifford Wolf
7b298479d4
Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 18:46:28 +01:00
Eddie Hung
fc87c010c5
autotest.sh to define _AUTOTB when test_autotb
2019-07-09 18:46:18 +01:00
Clifford Wolf
ef0823690c
Merge pull request #1146 from gsomlo/gls-test-abc-ext
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tests: use optional ABCEXTERNAL when specified
2019-07-09 18:44:57 +01:00
Eddie Hung
c864995343
Fix typo and comments
2019-07-09 10:38:07 -07:00
Eddie Hung
00d8a9dce2
Merge pull request #1170 from YosysHQ/eddie/fix_double_underscore
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Rename __builtin_bswap32 -> bswap32
2019-07-09 10:22:57 -07:00
Eddie Hung
c91cb73562
Merge remote-tracking branch 'origin/master' into xc7mux
2019-07-09 10:22:49 -07:00
Eddie Hung
c68b909210
synth_xilinx to call commands of synth -coarse directly
2019-07-09 10:21:54 -07:00
Eddie Hung
737340327f
Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""
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This reverts commit 7f964859ec
.
2019-07-09 10:15:02 -07:00
Eddie Hung
713337255e
Revert "Add "synth -keepdc" option"
2019-07-09 10:14:23 -07:00
Eddie Hung
5a0f2e43c7
Rename __builtin_bswap32 -> bswap32
2019-07-09 09:35:09 -07:00
Eddie Hung
bc84f7dd10
Fix spacing
2019-07-09 09:22:12 -07:00
Eddie Hung
667199d460
Fix spacing
2019-07-09 09:16:00 -07:00
Clifford Wolf
e95ce1f7af
Merge pull request #1168 from whitequark/bugpoint-processes
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Add support for processes in bugpoint
2019-07-09 16:59:43 +02:00
Clifford Wolf
a0787c12f0
Merge pull request #1169 from whitequark/more-proc-cleanups
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A new proc_prune pass
2019-07-09 16:59:18 +02:00
Clifford Wolf
38e942507e
Merge pull request #1163 from whitequark/more-case-attrs
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More support for case rule attributes
2019-07-09 16:57:16 +02:00
Clifford Wolf
ef07a313b4
Merge pull request #1162 from whitequark/rtlil-case-attrs
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Allow attributes on individual switch cases in RTLIL
2019-07-09 16:56:29 +02:00
Clifford Wolf
a429aedc0f
Merge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup
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Cleanup synth_xilinx SRL inference, make more consistent
2019-07-09 16:49:08 +02:00
whitequark
44bcb7a187
proc_prune: promote assigns to module connections when legal.
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This can pave the way for further transformations by exposing
identities that were previously hidden in a process to any pass that
uses SigMap. Indeed, this commit removes some ad-hoc logic from
proc_init that appears to have been tailored to the output of
genrtlil in favor of using `SigMap.apply()`. (This removal is not
optional, as the ad-hoc logic cannot cope with the result of running
proc_prune; a similar issue was fixed in proc_arst.)
2019-07-09 09:30:58 +00:00
whitequark
5fe0ffe30f
proc_prune: new pass.
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The proc_prune pass is similar in nature to proc_rmdead pass: while
proc_rmdead removes branches that never become active because another
branch preempts it, proc_prune removes assignments that never become
active because another assignment preempts them.
Genrtlil contains logic similar to the proc_prune pass, but their
purpose is different: genrtlil has to prune assignments to adapt
the semantics of blocking assignments in HDLs (latest assignment
wins) to semantics of assignments in RTLIL processes (assignment in
the most specific case wins). On the other hand proc_prune is
a general purpose RTLIL simplification that benefits all frontends,
even those not using the Yosys AST library.
The proc_prune pass is added to the proc script after proc_rmdead,
since it gives better results with fewer branches.
2019-07-09 09:30:58 +00:00
whitequark
f2fb958d44
bugpoint: add -assigns and -updates options.
2019-07-09 09:27:43 +00:00
whitequark
f7a14a5678
proc_clean: add -quiet option.
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This is useful for other passes that call it often, like bugpoint.
2019-07-09 09:27:43 +00:00
Eddie Hung
6951e32070
Decompose mux inputs in delay-orientated (rather than area) fashion
2019-07-08 23:51:13 -07:00
Eddie Hung
45da3ada7b
Do not call opt -mux_undef (part of -full) before muxcover
2019-07-08 23:49:16 -07:00
Eddie Hung
d4ab43d940
Add one more comment
2019-07-08 23:05:48 -07:00
Eddie Hung
939a225f92
Less thinking
2019-07-08 23:02:57 -07:00
Eddie Hung
de40453553
Reword
2019-07-08 22:56:19 -07:00
Eddie Hung
7f8c420cf7
Merge pull request #1166 from YosysHQ/eddie/synth_keepdc
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Add "synth -keepdc" option
2019-07-08 21:43:16 -07:00
Eddie Hung
7600ffe4bd
Merge branch 'master' of github.com:YosysHQ/yosys
2019-07-08 19:26:43 -07:00
Eddie Hung
7f964859ec
synth_xilinx to call "synth -run coarse" with "-keepdc"
2019-07-08 19:23:24 -07:00
Eddie Hung
9ac078be6f
Merge remote-tracking branch 'origin/eddie/synth_keepdc' into xc7mux
2019-07-08 19:21:53 -07:00
Eddie Hung
41d7d9d24b
Clarify script -scriptwire doc
2019-07-08 19:21:21 -07:00
Eddie Hung
fccabd0943
Add synth -keepdc to CHANGELOG
2019-07-08 19:15:37 -07:00
Eddie Hung
37b58f4324
Clarify 'wreduce -keepdc' doc
2019-07-08 19:15:07 -07:00
Eddie Hung
dd9771cbcd
Add synth -keepdc option
2019-07-08 19:14:54 -07:00
Eddie Hung
3f86407cc3
Map $__XILINX_SHIFTX in a more balanced manner
2019-07-08 17:06:35 -07:00
Eddie Hung
78914e2e0e
Capitalisation
2019-07-08 17:06:22 -07:00
Eddie Hung
baf47e496f
Add synth_xilinx -widemux recommended value
2019-07-08 17:04:39 -07:00
Eddie Hung
ede1ef61c5
Merge pull request #1164 from YosysHQ/eddie/muxcover_mux2
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Add muxcover -mux2=cost option
2019-07-08 14:34:37 -07:00
David Shah
22334fea40
Merge pull request #1160 from ZirconiumX/cyclone_v
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synth_intel: Warn about untested Quartus backend
2019-07-08 21:04:33 +01:00
Eddie Hung
b5072256f2
Update muxcover doc as per @ZirconiumX
2019-07-08 12:50:59 -07:00
Eddie Hung
895ca50173
Fixes for 2:1 muxes
2019-07-08 12:03:38 -07:00
Eddie Hung
0944acf3af
synth_xilinx -widemux=2 is minimum now
2019-07-08 11:29:21 -07:00
Eddie Hung
dbe1326573
Parametric muxcover costs as per @daveshah1
2019-07-08 11:08:20 -07:00
Eddie Hung
eb19abbb44
Merge remote-tracking branch 'origin/eddie/muxcover_mux2' into xc7mux
2019-07-08 11:00:31 -07:00
Eddie Hung
3681162c8d
atoi -> stoi
2019-07-08 11:00:06 -07:00