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23 Commits

Author SHA1 Message Date
Eddie Hung 8a11019d38 tests: tidy up testcase 2020-06-03 08:41:55 -07:00
Eddie Hung 1dce798dc5 tests: add ecp5 latch testcase with -abc9 2020-05-25 16:39:16 -07:00
Eddie Hung 38ee59184c tests: remove write_ilang 2020-04-20 15:42:29 -07:00
whitequark 93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style 
ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
 2020-04-10 14:51:01 +00:00
whitequark 763401fc82 ecp5: do not map FFRAM if explicitly requested otherwise. 2020-04-03 05:51:40 +00:00
Eddie Hung 717fb492b3 Update bug1630.ys to use -lut 4 instead of lut file 2020-02-27 10:17:29 -08:00
whitequark 081d9318bc ecp5: add support for both 1364.1 and LSE RAM/ROM attributes. 
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
  * LSE supports both `syn_ramstyle` and `syn_romstyle`.
  * Synplify only supports `syn_ramstyle`, with same values as LSE.
  * Synplify also supports `syn_rw_conflict_logic`, which is not
    documented as supported for LSE.

Limitations of the Yosys implementation:
  * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
    syntax to turn off insertion of transparency logic. There is
    currently no way to support multiple valued attributes in
    memory_bram. It is also not clear if that is a good idea, since
    it can cause sim/synth mismatches.
  * LSE/Synplify/1364.1 support block ROM inference from full case
    statements. Yosys does not currently perform this transformation.
  * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
    from the module to the inner memories. There is currently no way
    to do this in Yosys (attrmvcp only works on cells and wires).
 2020-02-06 16:52:51 +00:00
Eddie Hung b6a1f627b5 Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux 2020-02-05 10:47:31 -08:00
Marcelina Kościelnicka 34d2fbd2f9
Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
Eddie Hung 5aaa19f1ab Update tests with reduced area 2020-01-21 16:50:04 -08:00
Eddie Hung 565d349dc9 Add #1630 testcase 2020-01-13 21:27:53 -08:00
Eddie Hung 3df869cc7c Add testcase from #1459 2020-01-06 16:22:22 -08:00
Eddie Hung 713484fa66 Do not do call equiv_opt when no sim model exists 2019-12-31 18:40:30 -08:00
Eddie Hung c082329af3 Call equiv_opt with -multiclock and -assert 2019-12-31 18:39:32 -08:00
Eddie Hung c2c74f9bb0
Merge pull request #1599 from YosysHQ/eddie/retry_1588 
Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
 2019-12-30 10:01:02 -08:00
Eddie Hung 011f749ecf Update resource count 2019-12-28 02:15:11 -08:00
Eddie Hung d45869855c Add #1598 testcase 2019-12-27 16:44:57 -08:00
Eddie Hung caab66111e Rename memory tests to lutram, add more xilinx tests 2019-12-12 17:44:37 -08:00
Miodrag Milanovic 3e0ffe05a7 Fixed tests 2019-11-11 15:41:33 +01:00
Miodrag Milanovic 12383f37b2 Common memory test now shared 2019-10-18 12:33:35 +02:00
Miodrag Milanovic 5603595e5c Share common tests 2019-10-18 12:19:59 +02:00
Miodrag Milanovic 56f9482675 Fix path to yosys 2019-10-18 11:12:03 +02:00
Miodrag Milanovic c2ec7ca703 Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00