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3940 Commits

Author SHA1 Message Date
Clifford Wolf 777f2881d8 Add Verilog "automatic" keyword (ignored in synthesis) 2017-11-23 08:51:38 +01:00
Clifford Wolf e41dcaa759 Progress with new BTOR backend 2017-11-23 08:28:29 +01:00
Clifford Wolf 6ee305553a Add skeleton for new BTOR back-end 2017-11-23 06:38:57 +01:00
Clifford Wolf eceacdb9a3 Remove old BTOR back-end 2017-11-23 04:28:51 +01:00
Clifford Wolf 4782d59a3f
Merge pull request #455 from daveshah1/up5k 
Add UltraPlus specific cells to ice40 techlib
 2017-11-18 19:12:48 +01:00
David Shah 0505f1043c Remove unnecessary keep attributes 2017-11-18 17:53:21 +00:00
Clifford Wolf 5b6e52118c Accept real-valued delay values 2017-11-18 10:01:30 +01:00
Clifford Wolf a4195e83c7
Merge pull request #452 from cr1901/master 
Accommodate Windows-style paths during include-file processing.
 2017-11-18 09:58:40 +01:00
Clifford Wolf c01df04e32
Merge pull request #453 from dh73/master 
Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells
 2017-11-18 09:56:36 +01:00
David Shah 8ae73e60e2 Merge branch 'master' into up5k 2017-11-17 15:15:39 +00:00
Clifford Wolf 234726c655 Add "synth_ice40 -vpr" 2017-11-16 21:37:02 +01:00
David Shah f9f3ca5da0 Add some UltraPlus cells to ice40 techlib 2017-11-16 12:24:35 +00:00
dh73 acee813a5c Fixed the -vout flag to -vqm in examples/intel directory 2017-11-14 22:55:48 -06:00
William D. Jones abc5b4b8ce Accommodate Windows-style paths during include-file processing. 2017-11-14 16:16:24 -05:00
dh73 3fd1d61e2a Initial Cyclone 10 support 2017-11-08 22:45:21 -06:00
dh73 cf8cc50bf5 Merge https://github.com/cliffordwolf/yosys 2017-11-08 20:24:01 -06:00
dh73 1fc061d90c Organizing Speedster file names 2017-11-08 20:23:55 -06:00
Clifford Wolf 9ae25039fb Add support for editline as replacement for readline 2017-11-08 02:55:00 +01:00
Clifford Wolf 4f31cb6dad Add "ltp" command 2017-10-31 12:40:25 +01:00
Clifford Wolf 455c1c9d97 Fix SMT2 handling of initstate in sub-modules 2017-10-29 13:21:20 +01:00
Clifford Wolf c238f45ecf Fix memory corruption bug in opt_rmdff 2017-10-26 18:02:15 +02:00
Clifford Wolf 1e502ef5a0 Fix typo in opt_clean log message 2017-10-26 18:01:48 +02:00
Clifford Wolf 1170508264 Improve smtio performance by using reader thread, not writer thread 2017-10-26 01:01:55 +02:00
Clifford Wolf f513494f5f Use separate writer thread for talking to SMT solver to avoid read/write deadlock 2017-10-25 19:59:56 +02:00
Clifford Wolf 76326c163a Improve p_* functions in smtio.py 2017-10-25 15:45:32 +02:00
Clifford Wolf 104b9dc96b Disable OSX in .travis.yml 2017-10-25 15:17:29 +02:00
Clifford Wolf 9a038861c8 Add ENABLE_DEBUG config flag 2017-10-25 14:57:16 +02:00
Clifford Wolf af36755e0a Update ABC to hg rev f6838749f234 2017-10-25 14:51:59 +02:00
Clifford Wolf a8cf431d9c Remove vhdl2verilog 2017-10-25 14:50:22 +02:00
Clifford Wolf c672c321e3 Capsulate smt-solver read/write in separate functions 2017-10-25 13:37:11 +02:00
Clifford Wolf dd46d76394 Fix a bug in yosys-smtbmc in ROM handling 2017-10-25 13:05:14 +02:00
Clifford Wolf baddb017fe Remove PSL example from tests/sva/ 2017-10-20 13:16:24 +02:00
Clifford Wolf 0a31a0b3ae Remove all PSL support code from verific.cc 2017-10-20 13:14:04 +02:00
Clifford Wolf 309f8fe74f Merge pull request #437 from mithro/master 
Adding COPYING file with license information.
 2017-10-20 11:44:54 +02:00
Tim 'mithro' Ansell 19aa261527 Adding COPYING file with license information. 
This allows GitHub and other tools to detect the license info. Providing
a COPYING for LICENSE file is also pretty standard.
 2017-10-19 20:22:12 -04:00
Clifford Wolf 716dbc9274 Revert 90be0d8 as it causes endless loops for some designs 2017-10-14 11:57:25 +02:00
Clifford Wolf 1954c78ea7 Add "verific -vlog-libdir" 2017-10-13 20:23:19 +02:00
Clifford Wolf e7a3c47cc7 Add "verific -vlog-incdir" and "verific -vlog-define" 2017-10-13 20:12:51 +02:00
Clifford Wolf 05068af880 Update Verific README 2017-10-13 17:11:53 +02:00
Clifford Wolf d565bc4a82 Merge pull request #434 from Kmanfi/vector_fix 
Fix input vector for reduce cells.
 2017-10-12 12:16:47 +02:00
Kaj Tuomi 90be0d800b Fix input vector for reduce cells. 2017-10-12 13:05:10 +03:00
Clifford Wolf bc5cc4e103 Add Verific fairness/liveness support 2017-10-12 12:00:09 +02:00
Clifford Wolf 2b03a73a46 Update ABC to hg rev 6283c5d99b06 2017-10-11 13:58:51 +02:00
Clifford Wolf 12c10892e6 Merge branch 'master' of github.com:cliffordwolf/yosys 2017-10-10 15:16:45 +02:00
Clifford Wolf c10e96c9ec Start work on pre-processor for Verific SVA properties 2017-10-10 15:16:39 +02:00
Clifford Wolf 7c57d8fbb4 Rewrite ABC output to include proper net names in timing report 2017-10-10 13:32:58 +02:00
Clifford Wolf 142f4ca03a Add timing constraints to osu035 example 2017-10-10 13:32:04 +02:00
Clifford Wolf bc80426d45 Remove some dead code 2017-10-10 12:00:48 +02:00
Clifford Wolf caa78388cd Allow $past, $stable, $rose, $fell in $global_clock blocks 2017-10-10 11:59:32 +02:00
Clifford Wolf adf1754729 Add $shiftx support to verilog front-end 2017-10-07 13:40:54 +02:00