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1082 Commits

Author SHA1 Message Date
Eddie Hung c501aa5ee8 Signedness 2019-07-16 15:54:27 -07:00
Eddie Hung 6390c535ba Revert drop down to 24x16 multipliers for all 2019-07-16 14:30:25 -07:00
Eddie Hung 569cd66764 Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-07-16 14:18:36 -07:00
Eddie Hung 5d1ce04381 Add support for {A,B,P}REG in DSP48E1 2019-07-16 14:05:50 -07:00
David Shah d38df68d26 xilinx: Add correct signed behaviour to DSP48E1 model 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-16 17:53:08 +01:00
David Shah 95c8d27b0b xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed) 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-16 16:47:53 +01:00
David Shah 8da4c1ad82 mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-16 16:44:40 +01:00
David Shah 7a75f5f3ac mul2dsp: Fix indentation 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-16 16:19:32 +01:00
Eddie Hung fd5b3593d8 Do not swap if equals 2019-07-15 16:52:37 -07:00
Eddie Hung 5f00d335d4 Oops forgot these files 2019-07-15 15:03:15 -07:00
Eddie Hung 42f8e68e76 OUT port to Y in generic DSP 2019-07-15 14:45:47 -07:00
Eddie Hung 0c7ee6d0fa Move DSP mapping back out to dsp_map.v 2019-07-15 14:18:44 -07:00
Eddie Hung 91fcf034bc Only swap if B_WIDTH > A_WIDTH 2019-07-15 11:24:11 -07:00
Eddie Hung 1793e6018a Tidy up 2019-07-15 11:19:54 -07:00
Eddie Hung 20e3d2d9b0 Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim 2019-07-15 11:13:22 -07:00
Eddie Hung 146451a767 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-07-15 09:49:41 -07:00
Clifford Wolf 463f710066
Merge pull request #1183 from whitequark/ice40-always-relut 
synth_ice40: switch -relut to be always on
 2019-07-12 10:48:00 +02:00
whitequark b700a4b1c5 synth_ice40: switch -relut to be always on. 2019-07-11 20:18:41 +00:00
whitequark a8c5f7f41e synth_ice40: fix help text typo. NFC. 2019-07-11 20:18:41 +00:00
Eddie Hung 19c1c3cfa3
Merge pull request #1182 from koriakin/xc6s-bram 
synth_xilinx: Initial Spartan 6 block RAM inference support.
 2019-07-11 12:55:35 -07:00
Marcin Kościelnicki a9efacd01d xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado. 2019-07-11 21:13:12 +02:00
Marcin Kościelnicki ce250b341c synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-11 14:45:48 +02:00
Eddie Hung b33ecd2a74 Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little 2019-07-10 16:00:03 -07:00
Eddie Hung cea7441d8a Merge remote-tracking branch 'origin/master' into xc7dsp 2019-07-10 15:58:01 -07:00
Eddie Hung bb2144ae73
Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime 
Error out if -abc9 and -retime specified
 2019-07-10 14:38:13 -07:00
Eddie Hung 2f990a7319
Merge pull request #1148 from YosysHQ/xc7mux 
synth_xilinx to infer wide multiplexers using new '-widemux <min>' option
 2019-07-10 14:38:00 -07:00
Eddie Hung 6bbd286e03 Error out if -abc9 and -retime specified 2019-07-10 12:47:48 -07:00
Eddie Hung 58bb84e5b2 Add some spacing 2019-07-10 12:32:33 -07:00
Eddie Hung 521971e32e Add some ASCII art explaining mux decomposition 2019-07-10 12:20:04 -07:00
Eddie Hung e573d024a2 Call muxpack and pmux2shiftx before cmp2lut 2019-07-09 21:26:38 -07:00
Eddie Hung c55530b901 Restore opt_clean back to original place 2019-07-09 14:29:58 -07:00
Eddie Hung 5b48b18d29 Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6 2019-07-09 14:28:54 -07:00
David Shah 27b27b8781 synth_ecp5: Fix typo in copyright header 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-09 22:26:10 +01:00
Eddie Hung b1a048a703 Extend using A[1] to preserve don't care 2019-07-09 12:35:41 -07:00
Eddie Hung 93522b0ae1 Extend during mux decomposition with 1'bx 2019-07-09 10:59:37 -07:00
Eddie Hung c864995343 Fix typo and comments 2019-07-09 10:38:07 -07:00
Eddie Hung c91cb73562 Merge remote-tracking branch 'origin/master' into xc7mux 2019-07-09 10:22:49 -07:00
Eddie Hung c68b909210 synth_xilinx to call commands of synth -coarse directly 2019-07-09 10:21:54 -07:00
Eddie Hung 737340327f Revert "synth_xilinx to call "synth -run coarse" with "-keepdc"" 
This reverts commit 7f964859ec.
 2019-07-09 10:15:02 -07:00
Eddie Hung 713337255e
Revert "Add "synth -keepdc" option" 2019-07-09 10:14:23 -07:00
Eddie Hung bc84f7dd10 Fix spacing 2019-07-09 09:22:12 -07:00
Eddie Hung 667199d460 Fix spacing 2019-07-09 09:16:00 -07:00
Clifford Wolf a429aedc0f
Merge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup 
Cleanup synth_xilinx SRL inference, make more consistent
 2019-07-09 16:49:08 +02:00
Eddie Hung 6951e32070 Decompose mux inputs in delay-orientated (rather than area) fashion 2019-07-08 23:51:13 -07:00
Eddie Hung 45da3ada7b Do not call opt -mux_undef (part of -full) before muxcover 2019-07-08 23:49:16 -07:00
Eddie Hung d4ab43d940 Add one more comment 2019-07-08 23:05:48 -07:00
Eddie Hung 939a225f92 Less thinking 2019-07-08 23:02:57 -07:00
Eddie Hung de40453553 Reword 2019-07-08 22:56:19 -07:00
Eddie Hung 7f8c420cf7
Merge pull request #1166 from YosysHQ/eddie/synth_keepdc 
Add "synth -keepdc" option
 2019-07-08 21:43:16 -07:00
Eddie Hung 7f964859ec synth_xilinx to call "synth -run coarse" with "-keepdc" 2019-07-08 19:23:24 -07:00