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4511 Commits

Author SHA1 Message Date
Aman Goel 33cb5e05be
Merge pull request #4 from YosysHQ/master 
Merge with official repo
 2018-10-01 09:09:40 -04:00
Clifford Wolf 4d2917447c Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys 2018-09-30 18:44:07 +02:00
Clifford Wolf 9f9fe94b35 Fix handling of $past 2nd argument in read_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-30 18:43:35 +02:00
Clifford Wolf ac4000d855 Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys 2018-09-28 17:20:43 +02:00
Clifford Wolf 031824e38c Update to v2 YosysVS template 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-28 17:20:16 +02:00
tklam b86eb3deef fix bug: pass by reference 2018-09-26 17:57:39 +08:00
TK Lam 2b89074240 Fix issue #639 2018-09-26 16:11:45 +08:00
Udi Finkelstein 80a07652f2 Fixed issue #630 by fixing a minor typo in the previous commit 
(as well as a non critical minor code optimization)
 2018-09-25 00:32:57 +03:00
Clifford Wolf 8fde05dfa5 Add "read_verilog -noassert -noassume -assert-assumes" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-24 20:51:16 +02:00
Clifford Wolf eb452ffb28 Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-23 10:32:54 +02:00
Clifford Wolf 9659f7a99e Merge branch 'master' of https://github.com/mmicko/yosys into yosys-0.8-rc 2018-09-23 10:04:37 +02:00
Clifford Wolf 138ba71264 Update CHANGELOG 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-23 09:25:40 +02:00
Miodrag Milanovic 41affeeeb9 added prefix to FDirection constants, fixing windows build 2018-09-21 20:43:49 +02:00
Clifford Wolf 2867bf46a9 Update CHANGLELOG 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-21 16:27:07 +02:00
Clifford Wolf bf189122a8 Update Changelog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-21 13:55:20 +02:00
Clifford Wolf dc77ed1e88
Merge pull request #633 from mmicko/master 
Fix Cygwin build and document needed packages
 2018-09-19 15:08:31 +02:00
Clifford Wolf f1972b6c90
Merge pull request #631 from acw1251/master 
Fixed typo in "verilog_write" help message
 2018-09-19 15:07:28 +02:00
Miodrag Milanovic c5e9034834 Fix Cygwin build and document needed packages 2018-09-19 10:16:53 +02:00
acw1251 efac8a45a6 Fixed typo in "verilog_write" help message 2018-09-18 13:34:30 -04:00
Udi Finkelstein c693f595c5 Merge branch 'master' into pr_reg_wire_error 2018-09-18 01:27:01 +03:00
Udi Finkelstein f6fe73b31f Fixed remaining cases where we check fo wire reg/wire incorrect assignments 
on Yosys-generated assignments.
In this case, offending code was:

module top(input in, output out);
function func;
  input arg;
  func = arg;
endfunction
assign out = func(in);
endmodule
 2018-09-18 01:23:40 +03:00
Clifford Wolf 592a82c0ad
Merge pull request #625 from aman-goel/master 
Minor revision to -expose in setundef pass
 2018-09-14 12:36:13 +02:00
Clifford Wolf 1936d4408e
Merge pull request #627 from acw1251/master 
Fixed minor typo in "sim" help message
 2018-09-14 12:34:51 +02:00
acw1251 5fe16c25b8 Fixed minor typo in "sim" help message 2018-09-12 18:34:27 -04:00
Aman Goel 75c1f8d241 Minor revision to -expose in setundef pass 
Adds default value option as -undef when -expose used. Not having set the value mode set can cause the setundef pass to abort.
 2018-09-10 21:44:36 -04:00
Clifford Wolf 51f1bbeeb0 Add iCE40 SB_SPRAM256KA simulation model 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-10 11:57:24 +02:00
Clifford Wolf 12440fcc8f Add $lut support to Verilog back-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-06 00:18:01 +02:00
Clifford Wolf 5d9d22f66d Add "verific -L <int>" option 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-04 20:06:10 +02:00
Clifford Wolf 0b7a18470b Add "make ystests" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-30 12:26:26 +02:00
Miodrag Milanović d36d11936f Add GCC to osx deps (#620) 
* Add GCC to osx deps

* Force gcc-7 install
 2018-08-28 17:17:33 +02:00
Clifford Wolf cf2ea21899
Merge pull request #619 from mmicko/master 
Remove mercurial, since it is not needed anymore
 2018-08-28 13:37:11 +02:00
Miodrag Milanovic 92896a58be Remove mercurial, since it is not needed anymore 2018-08-28 13:11:41 +02:00
Clifford Wolf 373244c5ab
Merge pull request #618 from ucb-bar/firrtl+modules+shiftfixes 
Add support for modules.
 2018-08-28 12:04:49 +02:00
Jim Lawson e217c6c52f Merge branch 'master' into firrtl+modules+shiftfixes 2018-08-27 12:13:04 -07:00
Jim Lawson 380c6f0e97 Remove unused functions. 2018-08-27 10:18:33 -07:00
Jim Lawson 604b5d4e20
Merge pull request #3 from YosysHQ/master 
merge with YosysHQ
 2018-08-27 10:09:39 -07:00
Clifford Wolf ddc1761f1a Add "make coverage" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-27 14:22:21 +02:00
Clifford Wolf 9e845bd254 Add ENABLE_GCOV build option 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-27 13:27:05 +02:00
Clifford Wolf 96d79878b9
Merge pull request #617 from mmicko/master 
static link flag on main executable
 2018-08-25 16:40:55 +02:00
Miodrag Milanovic 306a010e19 static link flag on main executable 2018-08-25 16:20:44 +02:00
Jim Lawson 93d19dc2fb Add support for module instances. 
Don't pad logical operands to one bit.
Use operand width and signedness in $reduce_bool.
Shift amounts are unsigned and shouldn't be padded.
Group "is invalid" with the wire declaration, not its use (otherwise it is incorrectly wired to 0).
 2018-08-23 14:35:11 -07:00
Clifford Wolf 4d269f9b25
Merge pull request #610 from udif/udif_specify_round2 
More specify/endspecify fixes
 2018-08-23 14:43:25 +02:00
Clifford Wolf 92c2a04e19
Merge pull request #614 from udif/pr_disable_dump_ptr 
Added -no_dump_ptr flag for AST dump options in 'read_verilog'
 2018-08-23 14:41:41 +02:00
Udi Finkelstein 042b3074f8 Added -no_dump_ptr flag for AST dump options in 'read_verilog' 
This option disables the memory pointer display.
This is useful when diff'ing different dumps because otherwise the node pointers
makes every diff line different when the AST content is the same.
 2018-08-23 15:26:02 +03:00
Jim Lawson 2c0601eb6f
Merge pull request #1 from YosysHQ/master 
merge with YosysHQ master
 2018-08-22 08:42:34 -07:00
Clifford Wolf 408077769f Add "verific -work" help message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-22 17:22:24 +02:00
Clifford Wolf 4b02ee9162 Add Verific -work parameter 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-22 13:30:22 +02:00
Udi Finkelstein fbfc677df3 Fixed all known specify/endspecify issues, without breaking 'make test'. 
Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts,
due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses
 2018-08-20 17:27:45 +03:00
Udi Finkelstein 95241c8f4d Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v , 
(specify block ignored).
Must use 'read_verilog -defer' due to a parameter not assigned a default value.
 2018-08-20 00:08:08 +03:00
Clifford Wolf 05466790a6
Merge pull request #606 from cr1901/show-win 
`show` pass `-format` and `-viewer` improvements on Windows
 2018-08-19 15:25:46 +02:00