Filling out the hardware mapping sections, and actually highlighting the changes in schematics instead of just the memory block.
Also includes Part 4 of the coarse-grain rep, looking at `memory_collect` and putting the `synth_ice40 -top fifo -run :map_ram` command in its own (sub)section.
Includes a `no_rw_check` section label in `memory.rst` for reference (because I can't remember how to reference by heading).
Not sure about the opt output after map_ram section which has an open TODO, and the final steps section is also still open.
This change only matters for processes that weren't processed by
`proc_rmdead` for which follow-up cases after a default case are treated
differently in Verilog and RTLIL semantics.
The commit observer is a structure containing a callback that is invoked
whenever the `commit()` method changes a wire or a memory. This allows
code external to the compiled netlist to react to changes in the design
state in a very efficient way. One example of how this feature can be
used is an efficient implementation of record/replay.
Note that the VCD writer does not benefit from this feature because it
must be able to react to changes in any debug items and not just those
that contain design state.
While the VCD format separates the timescale and the timestep (likely
to allow representing the timestep with a small integer type), time in
CXXRTL is represented using a uniform 96-bit number, which allows for
a ±100 year range at femtosecond resolution.
The implementation uses `value<96>`, which provides fast arithmetic and
comparison operations, as well as conversion to/from a more common
representation of integer seconds plus femtoseconds.
Split hardware mapping from `fifo.ys` into `fifo_map.ys`. Reduces size of `fifo.out` log and allows separate yosys calls in the makefile.
Some tidy up and minor changes in `fifo.ys` for better discussion.
Filled out note on `clean` (changed from `opt_clean`) and introduced `;;`.
Highlighted `$memrd` and added a paragraph about it.
More detail on the flatten and merging of `fifo_reader` block.
Brief discussion on the changes from `$memrd` to `$memrd_v2`.
Split coarse grain representation into 4 parts, loosely: fsm/opt, other optimizations/techmap/memory_dff, DSPs, alumacc/memory -nomap.
Split hardware mapping into subsections as well: memory blocks (map_ram and map_ffram), arithmetic (map_gates), FFs (map_ffs), LUTs (map_luts and briefly abc), and other (map_cells and a note on hilomap and iopadmap).
Also add `-T` flag to Yosys call to remove footer from log output.
Added highlighting in (most) schematics.
Written down to end of coarse-grain, with a couple of TODOs for filling in gaps.
Includes `techmap_synth.rst` stub.
Fifo code based on SBY quick start.
Instead of showing the full design we are (currently) focusing on a single output (rdata), using `%ci*` to get the subcircuit it relies on.
Overall structure in place to match the iCE40 flow.
Still needs a new example design, and more text for the later sections (which the counter doesn't cover).
Updates code examples, removing `counter_outputs.ys` in favour of a single script. Also adds a .gitignore for the output file `synth.v`.
`example_synth.rst` still pending updated example.
Catherine
Miodrag Milanovic
github-actions[bot]
N. Engelhardt
hakan-demirli
Krystine Sherwin
hakan-demirli
Martin Povišer
Dag Lem
Claire Xen
Jannis Harder
Merry