yosys

mirror of https://github.com/YosysHQ/yosys.git

Author	SHA1	Message	Date
Clifford Wolf	ad9bbcbf40	Added $lut cells and abc lut mapping support	2013-07-23 16:19:34 +02:00
Clifford Wolf	32dbf7752d	Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v	2013-04-07 16:42:29 +02:00
Clifford Wolf	26f2439551	Tiny bugfix in simlib.v	2013-03-26 19:06:28 +01:00
Clifford Wolf	11789db206	More support code for $sr cells	2013-03-14 11:15:00 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00