Clifford Wolf
a27eeff573
Merge pull request #966 from YosysHQ/clifford/fix956
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Drive dangling wires with init attr with their init value
2019-04-30 18:08:41 +02:00
Clifford Wolf
5bc4de077a
Merge pull request #962 from YosysHQ/eddie/refactor_synth_xilinx
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Refactor synth_xilinx to auto-generate doc
2019-04-30 18:07:19 +02:00
Clifford Wolf
d9d50b0b0c
Merge branch 'master' into eddie/refactor_synth_xilinx
2019-04-30 17:00:34 +02:00
Clifford Wolf
58e991a0eb
Merge pull request #973 from christian-krieg/feature/python_bindings
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Feature/python bindings cleanup
2019-04-30 15:48:42 +02:00
Clifford Wolf
84f3a796e1
Include filename in "Executing Verilog-2005 frontend" message, fixes #959
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:37:46 +02:00
Clifford Wolf
9268cd1613
Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:19:10 +02:00
Clifford Wolf
9af825e31e
Add final loop variable assignment when unrolling for-loops, fixes #968
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:03:32 +02:00
Clifford Wolf
9d117eba9d
Add handling of init attributes in "opt_expr -undriven"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 14:46:12 +02:00
Benedikt Tutzer
dc06e3a28b
Merge branch 'master' of https://github.com/YosysHQ/yosys into feature/python_bindings
2019-04-30 13:22:33 +02:00
Benedikt Tutzer
124a284487
Cleaned up root directory
2019-04-30 13:19:04 +02:00
Marcin Kościelnicki
98e5a625c4
synth_xilinx: Add -nocarry and -nomux options.
2019-04-30 12:54:21 +02:00
Clifford Wolf
b515fd2d25
Add peepopt_muldiv, fixes #930
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 11:25:15 +02:00
Clifford Wolf
4306bebe58
pmgen progress
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 10:51:51 +02:00
Clifford Wolf
d2d402e625
Run "peepopt" in generic "synth" pass and "synth_ice40"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 08:10:37 +02:00
Clifford Wolf
bb4f3642de
Some pmgen reorg, rename peepopt.pmg to peepopt_shiftmul.pmg
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 08:04:22 +02:00
Clifford Wolf
58238da133
Progress in shiftmul peepopt pattern
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 07:59:39 +02:00
Clifford Wolf
314ff1e4ca
Merge pull request #960 from YosysHQ/eddie/equiv_opt_undef
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Add -undef option to equiv_opt, passed to equiv_induct
2019-04-29 13:54:26 +02:00
Clifford Wolf
8fde245ea2
Merge pull request #967 from olegendo/depfile_esc_spaces
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escape spaces with backslash when writing dep file
2019-04-29 13:48:52 +02:00
Clifford Wolf
ea547bcaa3
Add "peepopt" skeleton
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-29 13:38:56 +02:00
Clifford Wolf
9f792c599d
Add pmgen support for multiple patterns in one matcher
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-29 13:02:05 +02:00
Oleg Endo
4f15e7f00f
fix codestyle formatting
2019-04-29 19:20:33 +09:00
Clifford Wolf
32881a989c
Support multiple pmg files (right now just concatenated together)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-29 12:09:02 +02:00
Oleg Endo
e531fb203a
escape spaces with backslash when writing dep file
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filenames are sparated by spaces in the dep file. if a filename in the
dep file contains spaces they must be escaped, otherwise the tool that
reads the dep file will see multiple wrong filenames.
2019-04-29 16:13:34 +09:00
Clifford Wolf
754b1ee4b3
Drive dangling wires with init attr with their init value, fixes #956
2019-04-29 08:44:53 +02:00
Eddie Hung
acafcdc94d
Copy with 1'bx padding in $shiftx
2019-04-28 13:04:34 -07:00
Eddie Hung
e97178a888
WIP
2019-04-28 12:51:00 -07:00
Eddie Hung
af840bbc63
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
2019-04-28 12:36:04 -07:00
Eddie Hung
d855683917
Revert synth_xilinx 'fine' label more to how it used to be...
2019-04-26 16:53:16 -07:00
Eddie Hung
ea0e0722bb
Where did this check come from!?!
2019-04-26 15:35:34 -07:00
Eddie Hung
727eec04c5
Refactor synth_xilinx to auto-generate doc
2019-04-26 14:32:18 -07:00
Eddie Hung
1ea6d7920f
Cleanup ice40
2019-04-26 14:31:59 -07:00
Eddie Hung
159e7cc298
Add -undef option to equiv_opt, passed to equiv_induct
2019-04-26 11:16:48 -07:00
Eddie Hung
408161ea3a
Misspelling
2019-04-25 16:46:13 -07:00
Clifford Wolf
67005633e2
Add specify support to README
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 23:01:38 +02:00
Clifford Wolf
64925b4e8f
Improve $specrule interface
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:57:10 +02:00
Clifford Wolf
4575e4ad86
Improve $specrule interface
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:18:04 +02:00
Clifford Wolf
71c38d9de5
Add $specrule cells for $setup/$hold/$skew specify rules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
634482380c
Preserve $specify[23] cells
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
012c6af088
Allow $specify[23] cells in blackbox modules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
e807e88b60
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
846eb5ea98
Add $specify2/$specify3 support to write_verilog
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
0bf9d0087c
Add support for $assert/$assume/$cover to write_verilog
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
aec2475a9d
Add CellTypes support for $specify2 and $specify3
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
e1d73e03d3
Add InternalCellChecker support for $specify2 and $specify3
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
b232e027bf
Checking and fixing specify cells in genRTLIL
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
41b843c27b
Un-break default specify parser
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
3cc95fb4be
Add specify parser
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
a7e11261bd
Add $specify2 and $specify3 cells to simlib
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
b2020ab44f
Merge pull request #957 from YosysHQ/oai4fix
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Fixes for OAI4 cell implementation
2019-04-23 19:59:39 +02:00
David Shah
742c2f245d
Fixes for OAI4 cell implementation
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Fixes #955 and the underlying issue in #954
Signed-off-by: David Shah <dave@ds0.me>
2019-04-23 17:54:00 +01:00