riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
12,926 Commits 92 Branches 49 Tags 39 MiB
Commit Graph

12926 Commits

Author SHA1 Message Date
Catherine 5aaf1f1d39 cxxrtl: implement `value.get()` and `value.set()` for signed types. 2024-01-09 13:44:39 +00:00
Miodrag Milanovic c045c9a5c9 Update macOS to Ventura 2024-01-09 10:58:31 +01:00
github-actions[bot] 22370ad21e Bump version 2024-01-09 00:16:54 +00:00
N. Engelhardt 5a4db62870
Merge pull request #4111 from povik/verilog-back-nonpruned-case 
write_verilog: Handle edge case with non-pruned processes
 2024-01-08 16:38:56 +01:00
Martin Povišer 82fca50309 write_verilog: Handle edge case with non-pruned processes 
This change only matters for processes that weren't processed by
`proc_rmdead` for which follow-up cases after a default case are treated
differently in Verilog and RTLIL semantics.
 2024-01-06 17:05:02 +01:00
Martin Povišer 1ddb0892c1
Merge pull request #4101 from YosysHQ/micko/fix_init_order 
Fix Windows build by forcing initialization order, fixes #4068
 2024-01-06 10:46:34 +01:00
github-actions[bot] 30b795601c Bump version 2024-01-06 00:16:22 +00:00
Catherine f9dc1a2184 cxxrtl: fix comment wording. NFC 2024-01-05 20:41:16 +00:00
Catherine 3e358d9bfa cxxrtl: add a way to observe state changes during the commit step. 
The commit observer is a structure containing a callback that is invoked
whenever the `commit()` method changes a wire or a memory. This allows
code external to the compiled netlist to react to changes in the design
state in a very efficient way. One example of how this feature can be
used is an efficient implementation of record/replay.

Note that the VCD writer does not benefit from this feature because it
must be able to react to changes in any debug items and not just those
that contain design state.
 2024-01-05 19:02:00 +00:00
Catherine a94fafa8fe cxxrtl: add a representation of simulation timestamps. 
While the VCD format separates the timescale and the timestep (likely
to allow representing the timestep with a small integer type), time in
CXXRTL is represented using a uniform 96-bit number, which allows for
a ±100 year range at femtosecond resolution.

The implementation uses `value<96>`, which provides fast arithmetic and
comparison operations, as well as conversion to/from a more common
representation of integer seconds plus femtoseconds.
 2024-01-05 19:01:45 +00:00
Martin Povišer c72dc15f02
Merge pull request #4104 from daglem/struct-hierarchical-path 
Correct hierarchical path names for structs and unions
 2024-01-05 10:38:36 +01:00
Dag Lem 1bbea13f80 Correct hierarchical path names for structs and unions 2024-01-04 17:22:07 +01:00
Miodrag Milanovic 627fbc3477 Fix Windows build by forcing initialization order, fixes #4068 2024-01-02 11:26:48 +01:00
github-actions[bot] df65634e07 Bump version 2023-12-30 00:15:15 +00:00
Claire Xen 04fdb456f2
Merge pull request #4097 from YosysHQ/claire/constexpr 
Add constexpr hashlib default constructors
 2023-12-29 21:31:54 +01:00
Claire Xenia Wolf fb72dc1a40 Add constexpr hashlib default constructors 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2023-12-29 19:20:44 +01:00
github-actions[bot] ea7818d31b Bump version 2023-12-22 00:15:54 +00:00
Miodrag Milanović 86b8a1c5ae
Merge pull request #4087 from povik/lattice-dp8kc-fix 
lattice: Fix mapping onto DP8KC for data width 1 or 2
 2023-12-21 11:46:11 +01:00
Martin Povišer c028f25158 lattice: Disable broken port configuration in bram inference 2023-12-21 10:47:40 +01:00
Martin Povišer fc5c5172f8 lattice: Fix mapping onto DP8KC for data width 1 or 2 2023-12-20 23:42:12 +01:00
Miodrag Milanović a4ad7cb81a
Merge pull request #4049 from pepijndevos/patch-3 
Enable bram for Gowin
 2023-12-19 08:16:54 +01:00
N. Engelhardt d87bd7ca3f
Merge pull request #3887 from kivikakk/env-bash 
tests: use /usr/bin/env for bash.
 2023-12-18 16:33:35 +01:00
N. Engelhardt 78541be4d8
Merge pull request #3971 from povik/equiv_simple-fixes 
Fixes to `equiv_simple`
 2023-12-18 16:31:02 +01:00
N. Engelhardt 2615209dc1
Merge pull request #4078 from jix/smtbmc-cexenum-support 
Improvements to smtbmc/witness to support counter-example enumeration
 2023-12-18 16:20:52 +01:00
github-actions[bot] 70d35314db Bump version 2023-12-15 00:16:38 +00:00
Jannis Harder 94d7c22714 yosys-witness: Add aiw2yw --present-only to omit unused signals 2023-12-14 16:45:19 +01:00
Jannis Harder 3fab4d42ec smtbmc: Allow raw SMT-LIBv2 comamnds and expressions for --incremental 2023-12-14 16:44:21 +01:00
Jannis Harder 111085669b smtbmc: Use fewer smt commands while writing .yw traces 
Depending on the used solver and design this can be a signficant
performance improvement.
 2023-12-14 16:42:48 +01:00
Martin Povišer 449e3dbbd3 cxxrtl: Mask `bmux` result appropriately 2023-12-14 06:57:28 +00:00
github-actions[bot] 39fdde87a7 Bump version 2023-12-14 00:16:03 +00:00
Martin Povišer 112b11116d
Merge pull request #4072 from merryhime/cxxrtl-value-tests 
cxxrtl: Add simple tests for cxxrtl::value from cxxrtl runtime
 2023-12-13 18:11:26 +01:00
Merry 1dff3c83d9 tests/cxxrtl: Add -O2 2023-12-13 12:27:06 +00:00
Merry 29e0cc6acd cxxrtl: Add simple fuzzing tests for value 2023-12-13 12:21:44 +00:00
Merry d7cb6981b5 cxxrtl: Fix value::ctlz 2023-12-13 12:21:44 +00:00
Merry ded63bedd5 cxxrtl: Fix value::sshr 2023-12-13 12:11:57 +00:00
Merry ff53f3d2b6 cxxrtl: Fix value::shl 2023-12-13 12:02:30 +00:00
Henri Nurmi 1c8e58a736 cxxrtl: Fix formating 2023-12-13 06:08:01 +00:00
Henri Nurmi 79c0bfcb22 cxxrtl: Remove unnecessary length check 2023-12-13 06:08:01 +00:00
Henri Nurmi dbff694e3d cxxrtl: Use the base name of the interface file for the include directive 
Prior to this fix, the `CxxrtlBackend` used the entire path for the include
directive when a separated interface file is generated (via the `-header`
option). This commit updates the code to use the base name of the interface
file.

Since the C++11 standard is used by default, we cannot take advantage of
the `std::filesystem` to get the basename.
 2023-12-13 06:08:01 +00:00
github-actions[bot] 3ea6bca23e Bump version 2023-12-13 00:16:10 +00:00
Martin Povišer 5837fe8c91
Merge pull request #4067 from povik/cxxrtl-udivmod-fix 
cxxrtl: Fix `ctlz`, `udivmod`
 2023-12-12 21:22:25 +01:00
Martin Povišer 320e75a3e3
Merge pull request #4065 from daglem/fix-AST_SHIFT-AST_SHIFTX 
Respect the sign of the right operand of AST_SHIFT and AST_SHIFTX
 2023-12-12 11:47:29 +01:00
Martin Povišer 7bded221a7
Merge pull request #4066 from daglem/dump_vlog-more-ast-nodes 
Uncloak array expressions generated by read_verilog -dump_vlog2
 2023-12-12 11:30:07 +01:00
Martin Povišer 18d1907fa8 cxxrtl: Assert well-formedness of input to `udivmod` 2023-12-12 10:08:12 +01:00
Martin Povišer 6206a3af30 cxxrtl: Handle case of `Bits < 4` in formatting of values 2023-12-12 09:51:17 +01:00
Martin Povišer c848d98d91 cxxrtl: Fix `udivmod` logic 2023-12-11 22:11:35 +01:00
Martin Povišer bcf5e92389 cxxrtl: Fix `ctlz` implementation 2023-12-11 22:10:51 +01:00
Dag Lem 655921e851 Uncloak array expressions generated by read_verilog -dump_vlog2 
Explicit conversion of AST_TO_SIGNED, AST_TO_UNSIGNED, and AST_CAST_SIZE
makes it possible to reason about simplified array expressions.
 2023-12-11 19:12:35 +01:00
Dag Lem cda470d63e Respect the sign of the right operand of AST_SHIFT and AST_SHIFTX 
The $shift and $shiftx cells perform a left logical shift if the second
operand is negative. This change passes the sign of the second operand
of AST_SHIFT and AST_SHIFTX into $shift and $shiftx cells, respectively.
 2023-12-11 18:58:34 +01:00
Jannis Harder cca12d9d9b
Merge pull request #4055 from povik/sim-hier-prints 
sim: Print hierarchy for failed assertions
 2023-12-11 16:55:36 +01:00