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11 Commits

Author SHA1 Message Date
Lofty 9f7a55c99f intel_alm: M10K write-enable is negative-true 2022-03-09 20:18:06 +00:00
gatecat 5dba138c87 intel_alm: Add IO buffer insertion 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 22:37:06 +01:00
Dan Ravensloft 034b9ec716 intel: move Cyclone V support to intel_alm 2020-08-20 18:25:05 +02:00
Dan Ravensloft a2fb84fd0c intel_alm: direct M10K instantiation 
This reverts commit a3a90f6377.
 2020-07-27 15:39:06 +02:00
Lofty a3a90f6377 Revert "intel_alm: direct M10K instantiation" 
This reverts commit 09ecb9b2cf.
 2020-07-13 18:05:38 +02:00
Dan Ravensloft 09ecb9b2cf intel_alm: direct M10K instantiation 2020-07-05 23:28:59 +02:00
Dan Ravensloft b004f09018 intel_alm: DSP inference 2020-07-05 05:39:20 +02:00
Dan Ravensloft 83cde2d02b intel_alm: ABC9 sequential optimisations 2020-07-04 19:45:10 +02:00
Dan Ravensloft 5b779f7f4e intel_alm: direct LUTRAM cell instantiation 
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.

While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
 2020-05-07 21:03:13 +02:00
Dan Ravensloft 4ca5f9799b intel_alm: cleanup duplication 2020-04-24 11:26:48 +02:00
Dan Ravensloft 2e37e62e6b synth_intel_alm: alternative synthesis for Intel FPGAs 
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
 2020-04-15 11:40:41 +02:00