Clifford Wolf
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0bc95f1e04
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Added "yosys -D" feature
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2016-04-21 23:28:37 +02:00 |
Clifford Wolf
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825b99efc1
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Added "stat -liberty" for calculating chip area
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2016-02-04 12:26:13 +01:00 |
Clifford Wolf
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207736b4ee
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Import more std:: stuff into Yosys namespace
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2015-10-25 19:30:49 +01:00 |
Clifford Wolf
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6af8076967
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improvement in "stat"
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2015-10-24 21:56:53 +02:00 |
Clifford Wolf
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6c84341f22
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Fixed trailing whitespaces
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2015-07-02 11:14:30 +02:00 |
Clifford Wolf
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c6ae9ebb79
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Fixed "stat" handling of blackbox modules
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2015-02-14 22:36:34 +01:00 |
Clifford Wolf
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4569a747f8
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Renamed SIZE() to GetSize() because of name collision on Win32
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2014-10-10 17:07:24 +02:00 |
Clifford Wolf
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9dea161321
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sort cell types in "stat" output by name
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2014-10-03 19:21:04 +02:00 |
Clifford Wolf
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f9a307a50b
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namespace Yosys
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2014-09-27 16:17:53 +02:00 |
Clifford Wolf
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8927aa6148
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Removed $bu0 cell type
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2014-09-04 02:07:52 +02:00 |
Clifford Wolf
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fff12c719f
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Added "stat -width"
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2014-08-22 17:20:28 +02:00 |
Clifford Wolf
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10e5791c5e
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Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
Clifford Wolf
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4c4b602156
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Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-27 01:51:45 +02:00 |
Clifford Wolf
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f9946232ad
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Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-27 01:49:51 +02:00 |
Clifford Wolf
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3d95047ce2
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Bugfixes in new "stat" command
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2013-11-25 21:08:34 +01:00 |
Clifford Wolf
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4c7d6e63ec
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Added "stat" command
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2013-11-25 20:43:57 +01:00 |