Emil J. Tywoniak
785bd44da7
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
chunlin min
3db69b7a10
inline all tests. Add switch to remove init values as PolarFire DFFs do not support init
2024-07-08 17:03:03 -04:00
chunlin min
0afb5e28fb
cosmetic changes
2024-07-08 15:10:44 -04:00
chunlin min
af67c745c4
initialize argidx to 1
2024-07-08 11:41:41 -04:00
chunlin min
a0c9d10118
undo last change, to investigate dff_opt test failure
2024-07-08 11:30:52 -04:00
chunlin min
3c95a28dc2
fix compile warning
2024-07-08 11:13:53 -04:00
Tony Min
d41688f7d7
Revisions ( #4 )
...
* area should be 1 for all LUTs
* clean up macros
* add log_assert to fail noisily when encountering oddly configured DFF
* clean help msg
* flatten set to true by default
* update
* merge mult tests
* remove redundant test
* move all dsp tests to single file and remove redundant tests
* update ram tests
* add more dff tests
* fix c++20 compile errors
* add option to dump verilog
* default to use abc9
* remove -abc9 option since its the default now
---------
Co-authored-by: tony <minchunlin@gmail.com>
2024-07-08 10:57:16 -04:00
Tony Min
6fe0e00050
Add missing u sram init ( #3 )
...
add missing INIT for uSRAM
2024-07-04 16:39:10 -04:00
chunlin min
8e7ec2d660
add assertions for synth_microchip tests
2024-07-04 15:45:44 -04:00
chunlin min
e3c4791e5b
move microchip tests from techlibs/microchip/tests to tests/arch/microchip
2024-07-04 14:16:52 -04:00
chunlin min
19d3214861
use output reg instead of additional reg declaration
2024-07-04 14:13:26 -04:00
C77874
5ba06fd947
another typo
2024-07-04 10:33:59 -07:00
C77874
6b80e02d62
missed a few pf instances
2024-07-04 10:25:15 -07:00
C77874
c385421c17
rename options
2024-07-04 09:45:04 -07:00
C77874
d0cd01adfe
fixed typos, build with makefile succeeds
2024-07-04 09:33:58 -07:00
C77874
59e45be275
Merge branch 'mchp' of https://github.com/tony-min-1/yosys into change_filenames
2024-07-04 09:00:38 -07:00
C77874
0bb7d1373f
changes made to filenames + references
2024-07-04 08:53:41 -07:00