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another typo

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C77874 2024-07-04 10:33:59 -07:00
parent 6b80e02d62
commit 5ba06fd947
1 changed files with 1 additions and 1 deletions
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techlibs/microchip/tests/mac/mac.ys
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@ -18,7 +18,7 @@
read_verilog mac.v
# run the synth flow, specifies top module and additional parameters
synticrochip -top mac -abc9 -family polarfire -noiopad
synth_microchip -top mac -abc9 -family polarfire -noiopad
# write final outputfile
write_verilog -noexpr mac.vm