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5900 Commits

Author SHA1 Message Date
Clifford Wolf 0b7d648c6a Improve opt_clean handling of unused public wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 17:54:17 +02:00
Eddie Hung 4f0cb34495
Merge pull request #1136 from YosysHQ/xaig_ice40_wire_del 
abc9: Add wire delays to synth_ice40
 2019-06-26 08:51:11 -07:00
Clifford Wolf 1b49380f6b Improve BTOR2 handling of undriven wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 17:42:00 +02:00
David Shah 0dd850e655 abc9: Add wire delays to synth_ice40 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-26 11:39:44 +01:00
Clifford Wolf f6053b8810 Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 11:09:43 +02:00
Clifford Wolf 8e9ef891fe Do not clean up buffer cells with "keep" attribute, closes #1128 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 11:01:03 +02:00
Clifford Wolf b3c36b4448 Escape scope names starting with dollar sign in smtio.py 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 10:58:39 +02:00
whitequark 3d4102cfa4 Add more ECP5 Diamond flip-flops. 
This includes all I/O registers, and a few more regular FFs where it
was convenient.
 2019-06-26 01:57:29 +00:00
Eddie Hung 5db96b8aec Missing muxpack.o in Makefile 2019-06-25 10:38:42 -07:00
Eddie Hung 480a04cb3c Realistic delays for RAM32X1D too 2019-06-25 09:34:28 -07:00
Eddie Hung 6095357390 Add RAM32X1D box info 2019-06-25 09:34:19 -07:00
Eddie Hung 6f36ec8ecf Merge remote-tracking branch 'origin/master' into xaig 2019-06-25 09:33:11 -07:00
Eddie Hung ab6e8ce0f0 Add testcase from #335, fixed by #1130 2019-06-25 08:43:58 -07:00
Clifford Wolf add2d415fc
Merge pull request #1130 from YosysHQ/eddie/fix710 
memory_dff: walk through more than one mux for computing read enable
 2019-06-25 17:34:44 +02:00
Eddie Hung 42720ef6fe Fix spacing 2019-06-25 08:33:17 -07:00
Eddie Hung c4e4902098 Move only one consumer check outside of while loop 2019-06-25 08:29:55 -07:00
Eddie Hung 58629dc2ce
Merge pull request #1129 from YosysHQ/eddie/ram32x1d 
Add RAM32X1D support
 2019-06-25 08:22:57 -07:00
Clifford Wolf e754bce047
Merge pull request #1075 from YosysHQ/eddie/muxpack 
Add new "muxpack" command for packing chains of $mux cells
 2019-06-25 17:21:59 +02:00
Eddie Hung d2fed0a7f1 nullptr check 2019-06-25 06:06:32 -07:00
Eddie Hung 2f770b7400 Use LUT delays for dist RAM delays 2019-06-24 23:02:53 -07:00
Eddie Hung a19226c174 Fix for abc_scc_break is bus 2019-06-24 22:16:56 -07:00
Eddie Hung 5605002d8a More meaningful error message 2019-06-24 22:12:55 -07:00
Eddie Hung 4fadb471a3 Re-enable dist RAM boxes for ECP5 2019-06-24 22:12:50 -07:00
Eddie Hung a4a7e63d84 Revert "Re-enable dist RAM boxes for ECP5" 
This reverts commit ca0225fcfa.
 2019-06-24 22:10:28 -07:00
Eddie Hung babadf5938 Do not use log_id as it strips \\, also fix scc for |wire| > 1 2019-06-24 22:04:22 -07:00
Eddie Hung ca0225fcfa Re-enable dist RAM boxes for ECP5 2019-06-24 21:55:54 -07:00
Eddie Hung 152e682bd5 Add Xilinx dist RAM as comb boxes 2019-06-24 21:54:01 -07:00
Eddie Hung 49a762ba46 Fix abc9's scc breaker, also break on abc_scc_break attr 2019-06-24 21:53:18 -07:00
Eddie Hung 9dca024a30 Add tests/various/abc9.{v,ys} with SCC test 2019-06-24 21:52:53 -07:00
Eddie Hung cec2292b0b Merge remote-tracking branch 'origin/master' into xaig 2019-06-24 20:01:43 -07:00
Eddie Hung b7deaceadd Walk through as many muxes as exist for rd_en 2019-06-24 18:33:06 -07:00
Eddie Hung a701a2accf Add test 2019-06-24 18:32:58 -07:00
Eddie Hung efd04880db Add RAM32X1D support 2019-06-24 16:16:50 -07:00
Clifford Wolf e32cef4063
Merge pull request #1124 from mmicko/json_ports 
Add upto and offset to JSON ports
 2019-06-24 08:52:12 +02:00
Eddie Hung 4ddc0354c1 Merge remote-tracking branch 'origin/master' into eddie/muxpack 2019-06-22 14:40:55 -07:00
Eddie Hung 6027549464 Add comments to ecp5 box 2019-06-22 14:33:47 -07:00
Eddie Hung 792d0670c3 Add comment to xc7 box 2019-06-22 14:28:24 -07:00
Eddie Hung 63182ed57d Fix and cleanup ice40 boxes for carry in/out 2019-06-22 14:27:41 -07:00
Eddie Hung 7903ebe3e0 Carry in/out box ordering now move to end, not swap with end 2019-06-22 14:18:42 -07:00
Eddie Hung 65c022c257 Remove DFF and RAMD box info for now 2019-06-21 20:41:14 -07:00
Eddie Hung 8d18c256f0 Merge branch 'master' into xaig 2019-06-21 20:31:56 -07:00
Eddie Hung fb8fab4a29 Add 'muxcover -dmux=<cost>' and '-nopartial' to CHANGELOG 2019-06-21 20:30:24 -07:00
Eddie Hung 1abe93e48d Merge remote-tracking branch 'origin/master' into xaig 2019-06-21 17:43:29 -07:00
Eddie Hung 0f300e75c0 Fix CHANGELOG 2019-06-21 17:39:56 -07:00
Eddie Hung f2ead4334a Reduce log_debug spam in parse_xaiger() 2019-06-21 17:33:49 -07:00
Eddie Hung ad296d77ab Do not rename non LUT cells in abc9 2019-06-21 17:18:04 -07:00
Eddie Hung fddb027cab Replace assert with error message 2019-06-21 17:18:04 -07:00
Eddie Hung 7074ec9cd5 Add log_push()/log_pop() inside write_xaiger 2019-06-21 17:17:29 -07:00
Eddie Hung e01bab6c64
Merge pull request #1108 from YosysHQ/clifford/fix1091 
Add support for partial matches to muxcover
 2019-06-21 17:13:41 -07:00
Eddie Hung 65c1199acd One more workaround for gcc-4.8 2019-06-21 14:36:24 -07:00