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Merge branch 'master' into xaig

This commit is contained in:
Eddie Hung 2019-06-21 20:31:56 -07:00
parent 1abe93e48d fb8fab4a29
commit 8d18c256f0
1 changed files with 3 additions and 1 deletions
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@ -18,11 +18,13 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "equiv_opt" pass
- Added "shregmap -tech xilinx"
- Added "read_aiger" frontend
- Added "muxcover -mux{4,8,16}=<cost>"
- Added "muxcover -dmux=<cost>"
- Added "muxcover -nopartial"
- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
- Added "synth_xilinx -abc9" (experimental)
- Added "synth_ice40 -abc9" (experimental)
- Added "synth -abc9" (experimental)
- Extended "muxcover -mux{4,8,16}=<cost>"
- "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
- Fixed sign extension of unsized constants with 'bx and 'bz MSB