diff --git a/CHANGELOG b/CHANGELOG
index 192fc5a8d..0636e6bad 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -18,11 +18,13 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "equiv_opt" pass
     - Added "shregmap -tech xilinx"
     - Added "read_aiger" frontend
+    - Added "muxcover -mux{4,8,16}=<cost>"
+    - Added "muxcover -dmux=<cost>"
+    - Added "muxcover -nopartial"
     - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
     - Added "synth_xilinx -abc9" (experimental)
     - Added "synth_ice40 -abc9" (experimental)
     - Added "synth -abc9" (experimental)
-    - Extended "muxcover -mux{4,8,16}=<cost>"
     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
     - Fixed sign extension of unsized constants with 'bx and 'bz MSB