riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
14,541 Commits 92 Branches 49 Tags 38 MiB
Commit Graph

14541 Commits

Author SHA1 Message Date
Miodrag Milanovic aaa5347494 Release version 0.48 2024-12-11 08:35:36 +01:00
github-actions[bot] 1f6153a55a Bump version 2024-12-11 00:22:54 +00:00
Martin Povišer 4bd6061709
Merge pull request #4799 from povik/wrapcell-unused 
wrapcell: Optionally track unused outputs
 2024-12-10 21:16:28 +01:00
Martin Povišer 3ce7283e12
Merge pull request #4809 from povik/rm-global-tcl-h 
kernel: Remove global `tcl.h` include
 2024-12-10 20:36:34 +01:00
Martin Povišer 86fad8f6f5
Merge pull request #4803 from povik/write_verilog-buf 
write_verilog: Use assign for `$buf`
 2024-12-10 20:10:58 +01:00
Martin Povišer f7ad003a6f
Merge pull request #4802 from povik/abc9-box-repeat 
Adjust `abc9_ops -prep_box` to allow repeated invocation
 2024-12-10 20:08:17 +01:00
Martin Povišer ea38fcca5e
Merge pull request #4737 from povik/abc_new-design-boxes 
Support `abc9_box` on ordinary modules in abc_new
 2024-12-10 20:07:56 +01:00
Martin Povišer e9c7967d1e
Merge pull request #4804 from povik/read_liberty-comb-cells 
read_liberty: Revisit for abc9 whiteboxes
 2024-12-10 17:50:21 +01:00
Emil J aed32a1df4
Merge pull request #4810 from YosysHQ/emil/fix-dfflibmap-test 
tests: fix dfflibmap test
 2024-12-10 17:46:11 +01:00
Emil J. Tywoniak 55dcf0e200 tests: fix dfflibmap test - false negative conflict multiple -liberty vs enable inference 2024-12-10 15:48:23 +01:00
Martin Povišer 48c8d70a45 wrapcell: Test `check -assert` post wrapping 2024-12-10 15:13:31 +01:00
Martin Povišer 3cd01a57cd wrapcell: Add comments, const qualifier 2024-12-10 15:13:31 +01:00
Martin Povišer 0bb139dc25 abc_new: Fix help crash 2024-12-10 14:27:55 +01:00
Martin Povišer 6b343c2600 aiger2: Clean debug print 2024-12-10 14:27:55 +01:00
Martin Povišer 559209c856 abc_new: Fix PI confusion in whitebox model export 2024-12-10 14:27:29 +01:00
Martin Povišer 2a3f60bc06 abc_new: Support `abc9_box` mode on ordinary design hierarchy 
Previously the `abc9_box` mode was reserved to modules with the
`blackbox` or `whitebox` attribute. Allow `abc9_box` on ordinary modules
when doing hierarchical synthesis.
 2024-12-10 14:27:29 +01:00
Martin Povišer 285f24d764 abc_new: Support per-module script override 2024-12-10 14:27:29 +01:00
Martin Povišer 495a7805ec aiger2: Support `$extern:` hierarchy 
`$extern:...` modules inserted by `techmap -extern` are special in the
regard that they have a private ID (starting with a dollar sign) but are
not an internal cell. Support those modules in xaiger export.
 2024-12-10 14:27:29 +01:00
Martin Povišer 1f718e3ab6 kernel: Remove global `tcl.h` include 
In commit ac988cf we made sure to undefine the CONST/VOID macros left
defined by `tcl.h`, but this in turn makes it an issue to include
additional Tcl headers later on (see issue #4808).

One way out is to avoid a global `tcl.h` include. In the process we drop
support for Tcl-enabled MXE builds, which were likely broken anyway due
to the additional Tcl APIs used from `tclapi.cc`.
 2024-12-10 13:49:08 +01:00
Emil J 87736a2bf9
Merge pull request #4807 from YosysHQ/emil/dfflibmap-test-dffe 
dfflibmap: cover enable inference with test
 2024-12-10 12:41:11 +01:00
Martin Povišer b0708a38bf
Merge pull request #4678 from povik/tcl-rtlil-api 
Start Tcl design inspection methods
 2024-12-09 15:44:58 +01:00
Martin Povišer a353b8fff0 read_liberty: Directly set `abc9_box` on fitting cells 2024-12-09 15:43:41 +01:00
Martin Povišer 9161377c5a wrapcell: Fix help 2024-12-09 15:40:33 +01:00
Miodrag Milanović d0f239a0c4
Merge pull request #4806 from YosysHQ/micko/verific_blackbox 
verific: Disable module existence check during static elaboration
 2024-12-09 15:13:34 +01:00
Martin Povišer 481162b848
Merge pull request #4800 from povik/portarcs-fix 
Fix portarcs edge cases
 2024-12-09 15:13:15 +01:00
Emil J. Tywoniak 681b678417 dfflibmap: cover enable inference with test 2024-12-09 14:18:08 +01:00
Miodrag Milanović f4ddbc3994
Merge pull request #4771 from pepijndevos/famxtra 
gowin: split cells_xtra by family
 2024-12-08 19:46:36 +01:00
github-actions[bot] fa0c311862 Bump version 2024-12-07 00:22:16 +00:00
Miodrag Milanovic 05398889ad Add verific verilog test cases for blackboxes 2024-12-06 16:13:25 +01:00
Miodrag Milanovic 7d4aff618f verific: Disable module existence check during static elaboration 2024-12-06 15:59:09 +01:00
Miodrag Milanović 2ca611b4f4
Merge pull request #4778 from YosysHQ/setenv_pass 
add setenv pass
 2024-12-06 11:55:44 +01:00
Miodrag Milanović 4a755f53a5
Merge pull request #4805 from YosysHQ/hash_scopeindex 
add hash method to scopeindex cursor
 2024-12-06 11:48:55 +01:00
N. Engelhardt 8557455411 handle quotes and check return value 2024-12-06 11:25:45 +01:00
Miodrag Milanovic 1b403b82d7 Handle setting environment on Windows 2024-12-06 11:25:45 +01:00
N. Engelhardt 8b0f665cc5 add setenv pass 2024-12-06 11:25:43 +01:00
N. Engelhardt 2a744b4b82 add hash method to scopeindex cursor 2024-12-06 11:18:39 +01:00
github-actions[bot] b66897e9b9 Bump version 2024-12-06 00:22:38 +00:00
Martin Povišer 4cdca66579
Merge pull request #4801 from povik/aiger2-rm-print 
read_xaiger2: Rm debug print
 2024-12-05 18:41:16 +01:00
Martin Povišer cf0a583f40 read_xaiger2: Rm debug print 2024-12-05 18:33:20 +01:00
Martin Povišer f3f8037328 abc9_ops: Allow no arcs on box w/o inputs or w/o outputs 2024-12-05 18:32:41 +01:00
Martin Povišer 481d596c43 abc9_ops -prep_box: Adjust for repeated invocation 
`abc9_ops -prep_box` command interprets the `abc9_box` attribute and
prepares a .box file for ABC consumption. Previously this command was
removing the attribute as it was processing each module which prevented
repeated invocation of this command unless the box definitions were
refreshed from a source file.

Also the command was keeping existing `abc9_box_id` attributes instead
of overwriting them with values from a new number sequence.

Change both behaviors to allow repeated invocations of the command on
the same design.
 2024-12-05 18:32:41 +01:00
Martin Povišer 5dffdd229c read_liberty: Redo unit delay; add `simple_comb_cell` attr 2024-12-05 18:31:24 +01:00
Martin Povišer e7b21d2706 write_verilog: Use assign for `$buf` 2024-12-05 18:28:23 +01:00
Martin Povišer f4f65493a1 portarcs: Fix confusing disconnected and zero-delay case 2024-12-05 18:27:44 +01:00
Martin Povišer 2c66557d22 portarcs: Fix for case of unused gates 2024-12-05 18:27:43 +01:00
Martin Povišer d57d21e566 wrapcell: Optionally track unused outputs 2024-12-05 18:16:53 +01:00
github-actions[bot] 66734f522d Bump version 2024-12-05 00:22:38 +00:00
KrystalDelusion 4418f92099
Merge pull request #4731 from YosysHQ/docs-preview-noguidelines 
Integrate guidelines folder into documentation
 2024-12-05 09:59:36 +13:00
Krystine Sherwin 40af327cb6
Docs/installation: Drop resolved todos 2024-12-05 09:21:13 +13:00
Krystine Sherwin 6b3f2fdc8d
Docs: Installation instructions 
Add warning for Cygwin.
Add commented out instructions for MSYS2 that I tried to get to work but ran into build errors.
 2024-12-05 09:21:13 +13:00