mirror of https://github.com/YosysHQ/yosys.git
wrapcell: Optionally track unused outputs
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66734f522d
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d57d21e566
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@ -18,12 +18,37 @@
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*/
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#include "kernel/yosys.h"
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#include "kernel/celltypes.h"
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#include "kernel/sigtools.h"
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#include "backends/rtlil/rtlil_backend.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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std::optional<std::string> format(std::string fmt, const dict<IdString, Const> ¶meters)
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bool has_fmt_field(std::string fmt, std::string field_name)
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{
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auto it = fmt.begin();
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while (it != fmt.end()) {
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if (*it == '{') {
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it++;
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auto beg = it;
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while (it != fmt.end() && *it != '}') it++;
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if (it == fmt.end())
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return false;
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if (std::string(beg, it) == field_name)
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return true;
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}
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it++;
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}
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return false;
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}
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struct ContextData {
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std::string unused_outputs;
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};
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std::optional<std::string> format(std::string fmt, const dict<IdString, Const> ¶meters,
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ContextData &context)
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{
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std::stringstream result;
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@ -38,13 +63,19 @@ std::optional<std::string> format(std::string fmt, const dict<IdString, Const> &
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return {};
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}
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auto id = RTLIL::escape_id(std::string(beg, it));
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if (!parameters.count(id)) {
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log("Parameter %s referenced in format string '%s' not found\n", log_id(id), fmt.c_str());
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return {};
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}
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std::string param_name = {beg, it};
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RTLIL_BACKEND::dump_const(result, parameters.at(id));
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if (param_name == "%unused") {
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result << context.unused_outputs;
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} else {
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auto id = RTLIL::escape_id(std::string(beg, it));
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if (!parameters.count(id)) {
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log("Parameter %s referenced in format string '%s' not found\n", log_id(id), fmt.c_str());
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return {};
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}
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RTLIL_BACKEND::dump_const(result, parameters.at(id));
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}
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} else {
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result << *it;
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}
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@ -54,6 +85,44 @@ std::optional<std::string> format(std::string fmt, const dict<IdString, Const> &
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return {result.str()};
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}
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struct Chunk {
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IdString port;
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int base, len;
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Chunk(IdString id, int base, int len)
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: port(id), base(base), len(len) {}
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IdString format(Cell *cell)
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{
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if (len == cell->getPort(port).size())
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return port;
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else if (len == 1)
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return stringf("%s[%d]", port.c_str(), base);
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else
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return stringf("%s[%d:%d]", port.c_str(), base + len - 1, base);
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}
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SigSpec sample(Cell *cell)
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{
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return cell->getPort(port).extract(base, len);
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}
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};
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std::vector<Chunk> collect_chunks(std::vector<std::pair<IdString, int>> bits)
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{
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std::vector<Chunk> ret;
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std::sort(bits.begin(), bits.end());
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for (auto it = bits.begin(); it != bits.end();) {
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auto sep = it + 1;
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for (; sep != bits.end() &&
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sep->first == it->first &&
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sep->second == (sep - 1)->second + 1; sep++);
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ret.emplace_back(it->first, it->second, sep - it);
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it = sep;
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}
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return ret;
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}
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struct WrapcellPass : Pass {
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WrapcellPass() : Pass("wrapcell", "wrap individual cells into new modules") {}
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@ -68,6 +137,10 @@ struct WrapcellPass : Pass {
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log("parameter values as specified in curly brackets. If the named module already\n");
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log("exists, it is reused.\n");
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log("\n");
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log("If the template contains the special string '{%unused}', the command tracks\n");
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log("unused output ports -- specialized wrapper modules will be generated per every\n");
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log("set of unused ports as appearing on a selected cell.\n");
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log("\n");
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log(" -setattr <attribute-name>\n");
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log(" set the given boolean attribute on each created wrapper module\n");
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log("\n");
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@ -114,35 +187,80 @@ struct WrapcellPass : Pass {
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CellTypes ct;
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ct.setup();
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bool tracking_unused = has_fmt_field(name_fmt, "%unused");
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for (auto module : d->selected_modules()) {
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for (auto cell : module->selected_cells()) {
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std::optional<std::string> unescaped_name = format(name_fmt, cell->parameters);
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if (!unescaped_name)
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log_error("Formatting error when processing cell '%s' in module '%s'\n",
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log_id(cell), log_id(module));
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SigPool unused;
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IdString name = RTLIL::escape_id(unescaped_name.value());
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if (d->module(name)) {
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cell->type = name;
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cell->parameters.clear();
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continue;
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for (auto wire : module->wires())
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if (wire->has_attribute(ID::unused_bits)) {
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std::string str = wire->get_string_attribute(ID::unused_bits);
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for (auto it = str.begin(); it != str.end();) {
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auto sep = it;
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for (; sep != str.end() && *sep != ' '; sep++);
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unused.add(SigBit(wire, std::stoi(std::string(it, sep))));
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for (it = sep; it != str.end() && *it == ' '; it++);
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}
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}
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for (auto cell : module->selected_cells()) {
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Module *subm;
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Cell *subcell;
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if (!ct.cell_known(cell->type))
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log_error("Non-internal cell type '%s' on cell '%s' in module '%s' unsupported\n",
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log_id(cell->type), log_id(cell), log_id(module));
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Module *subm = d->addModule(name);
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Cell *subcell = subm->addCell("$1", cell->type);
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std::vector<std::pair<IdString, int>> unused_outputs, used_outputs;
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for (auto conn : cell->connections()) {
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Wire *w = subm->addWire(conn.first, conn.second.size());
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if (ct.cell_output(cell->type, w->name))
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w->port_output = true;
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else
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w->port_input = true;
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subcell->setPort(conn.first, w);
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if (ct.cell_output(cell->type, conn.first))
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for (int i = 0; i < conn.second.size(); i++) {
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if (tracking_unused && unused.check(conn.second[i]))
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unused_outputs.emplace_back(conn.first, i);
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else
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used_outputs.emplace_back(conn.first, i);
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}
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}
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ContextData context;
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if (!unused_outputs.empty()) {
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context.unused_outputs += "_unused";
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for (auto chunk : collect_chunks(unused_outputs))
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context.unused_outputs += "_" + RTLIL::unescape_id(chunk.format(cell));
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}
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std::optional<std::string> unescaped_name = format(name_fmt, cell->parameters, context);
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if (!unescaped_name)
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log_error("Formatting error when processing cell '%s' in module '%s'\n",
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log_id(cell), log_id(module));
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IdString name = RTLIL::escape_id(unescaped_name.value());
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if (d->module(name))
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goto replace_cell;
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subm = d->addModule(name);
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subcell = subm->addCell("$1", cell->type);
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for (auto conn : cell->connections()) {
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if (ct.cell_output(cell->type, conn.first)) {
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subcell->setPort(conn.first, SigSpec(RTLIL::Sm, conn.second.size()));
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} else {
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Wire *w = subm->addWire(conn.first, conn.second.size());
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w->port_input = true;
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subcell->setPort(conn.first, w);
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}
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}
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for (auto chunk : collect_chunks(used_outputs)) {
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Wire *w = subm->addWire(chunk.format(cell), chunk.len);
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w->port_output = true;
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subcell->connections_[chunk.port].replace(chunk.base, w);
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}
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for (auto chunk : collect_chunks(unused_outputs)) {
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Wire *w = subm->addWire(chunk.format(cell), chunk.len);
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subcell->connections_[chunk.port].replace(chunk.base, w);
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}
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subcell->parameters = cell->parameters;
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subm->fixup_ports();
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@ -150,7 +268,7 @@ struct WrapcellPass : Pass {
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if (rule.value_fmt.empty()) {
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subm->set_bool_attribute(rule.name);
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} else {
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std::optional<std::string> value = format(rule.value_fmt, cell->parameters);
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std::optional<std::string> value = format(rule.value_fmt, cell->parameters, context);
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if (!value)
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log_error("Formatting error when processing cell '%s' in module '%s'\n",
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@ -160,8 +278,20 @@ struct WrapcellPass : Pass {
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}
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}
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cell->type = name;
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replace_cell:
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cell->parameters.clear();
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dict<IdString, SigSpec> new_connections;
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for (auto conn : cell->connections())
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if (!ct.cell_output(cell->type, conn.first))
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new_connections[conn.first] = conn.second;
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for (auto chunk : collect_chunks(used_outputs))
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new_connections[chunk.format(cell)] = chunk.sample(cell);
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cell->type = name;
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cell->connections_ = new_connections;
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}
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}
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}
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@ -23,3 +23,33 @@ select -assert-count 1 top/t:OR_3_4_4
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select -assert-none top/t:OR_2_3_3 top/t:OR_3_4_4 %% top/t:* %D
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select -assert-mod-count 2 OR_2_3_3 OR_3_4_4
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select -assert-mod-count 2 A:bar=w3 A:bar=w4
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design -reset
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read_verilog <<EOF
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module top(
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input [1:0] a,
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input [2:0] b,
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output [2:0] y,
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input [2:0] a2,
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input [3:0] b2,
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output [3:0] y2,
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input [1:0] a3,
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input [2:0] b3,
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output [2:0] y3
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);
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assign y = a | (*keep*) b;
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assign y2 = a2 | (*keep*) b2;
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wire [2:0] y3_ = a3 | (*keep*) b3;
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assign y3 = {y3_[2], y3_[0]};
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endmodule
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EOF
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opt_clean
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wreduce
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wrapcell -setattr foo -formatattr bar w{Y_WIDTH} -name OR_{A_WIDTH}_{B_WIDTH}_{Y_WIDTH}{%unused}
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select -assert-count 1 top/t:OR_2_3_3
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select -assert-count 1 top/t:OR_2_3_3_unused_Y[1]
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select -assert-count 1 top/t:OR_3_4_4
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select -assert-none top/t:OR_2_3_3 top/t:OR_3_4_4 top/t:OR_2_3_3_unused_Y[1] %% top/t:* %D
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select -assert-mod-count 2 OR_2_3_3 OR_3_4_4
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select -assert-mod-count 3 A:bar=w3 A:bar=w4
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