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Merge pull request #4737 from povik/abc_new-design-boxes 

Support `abc9_box` on ordinary modules in abc_new
This commit is contained in:
Martin Povišer 2024-12-10 20:07:56 +01:00 committed by GitHub
parent e9c7967d1e 0bb139dc25
commit ea38fcca5e
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GPG Key ID: B5690EEEBB952194
4 changed files with 57 additions and 11 deletions
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12
backends/aiger2/aiger.cc
View File

@ -832,12 +832,8 @@ struct XAigerAnalysis : Index<XAigerAnalysis, int, 0, 0> {
return false;
Cell *driver = bit.wire->driverCell();
if (!driver->type.isPublic())
return false;
Module *mod = design->module(driver->type);
log_assert(mod);
if (!mod->has_attribute(ID::abc9_box_id))
if (!mod || !mod->has_attribute(ID::abc9_box_id))
return false;
int max = 1;
@ -870,7 +866,7 @@ struct XAigerAnalysis : Index<XAigerAnalysis, int, 0, 0> {
HierCursor cursor;
for (auto box : top_minfo->found_blackboxes) {
Module *def = design->module(box->type);
if (!box->type.isPublic() || (def && !def->has_attribute(ID::abc9_box_id)))
if (!(def && def->has_attribute(ID::abc9_box_id)))
for (auto &conn : box->connections_)
if (box->output(conn.first))
for (auto bit : conn.second)
@ -885,7 +881,7 @@ struct XAigerAnalysis : Index<XAigerAnalysis, int, 0, 0> {
for (auto box : top_minfo->found_blackboxes) {
Module *def = design->module(box->type);
if (!box->type.isPublic() || (def && !def->has_attribute(ID::abc9_box_id)))
if (!(def && def->has_attribute(ID::abc9_box_id)))
for (auto &conn : box->connections_)
if (box->input(conn.first))
for (auto bit : conn.second)
@ -1106,7 +1102,7 @@ struct XAigerWriter : AigerWriter {
holes_module->ports.push_back(w->name);
holes_pis.push_back(w);
}
in_conn.append(holes_pis[i]);
in_conn.append(holes_pis[holes_pi_idx]);
holes_pi_idx++;
}
holes_wb->setPort(port_id, in_conn);

1
frontends/aiger2/xaiger.cc
View File

@ -203,7 +203,6 @@ struct Xaiger2Frontend : public Frontend {
/* unused box_id = */ read_be32(*f);
auto box_seq = read_be32(*f);
log("box_seq=%d boxes.size=%d\n", box_seq, (int) boxes.size());
log_assert(box_seq < boxes.size());
auto [cell, def] = boxes[box_seq];

3
passes/techmap/abc9_ops.cc
View File

@ -1078,7 +1078,8 @@ void prep_box(RTLIL::Design *design)
}
ss << log_id(module) << " " << module->attributes.at(ID::abc9_box_id).as_int();
ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
bool has_model = module->get_bool_attribute(ID::whitebox) || !module->get_bool_attribute(ID::blackbox);
ss << " " << (has_model ? "1" : "0");
ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
bool first = true;

52
passes/techmap/abc_new.cc
View File

@ -19,10 +19,29 @@
#include "kernel/register.h"
#include "kernel/rtlil.h"
#include "kernel/utils.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
std::vector<Module*> order_modules(Design *design, std::vector<Module *> modules)
{
std::set<Module *> modules_set(modules.begin(), modules.end());
TopoSort<Module*> sort;
for (auto m : modules) {
sort.node(m);
for (auto cell : m->cells()) {
Module *submodule = design->module(cell->type);
if (modules_set.count(submodule))
sort.edge(submodule, m);
}
}
log_assert(sort.sort());
return sort.sorted;
}
struct AbcNewPass : public ScriptPass {
AbcNewPass() : ScriptPass("abc_new", "(experimental) use ABC for SC technology mapping (new)")
{
@ -101,6 +120,15 @@ struct AbcNewPass : public ScriptPass {
}
if (check_label("prep_boxes")) {
if (!help_mode) {
for (auto mod : active_design->selected_whole_modules_warn()) {
if (mod->get_bool_attribute(ID::abc9_box)) {
mod->set_bool_attribute(ID::abc9_box, false);
mod->set_bool_attribute(ID(abc9_deferred_box), true);
}
}
}
run("box_derive");
run("abc9_ops -prep_box");
}
@ -109,7 +137,8 @@ struct AbcNewPass : public ScriptPass {
std::vector<Module *> selected_modules;
if (!help_mode) {
selected_modules = active_design->selected_whole_modules_warn();
selected_modules = order_modules(active_design,
active_design->selected_whole_modules_warn());
active_design->selection_stack.emplace_back(false);
} else {
selected_modules = {nullptr};
@ -131,15 +160,36 @@ struct AbcNewPass : public ScriptPass {
active_design->selection().select(mod);
}
std::string script_save;
if (!help_mode && mod->has_attribute(ID(abc9_script))) {
script_save = active_design->scratchpad_get_string("abc9.script");
active_design->scratchpad_set_string("abc9.script",
mod->get_string_attribute(ID(abc9_script)));
}
run(stringf(" abc9_ops -write_box %s/input.box", tmpdir.c_str()));
run(stringf(" write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir.c_str(), tmpdir.c_str()));
run(stringf(" abc9_exe %s -cwd %s -box %s/input.box", exe_options.c_str(), tmpdir.c_str(), tmpdir.c_str()));
run(stringf(" read_xaiger2 -sc_mapping -module_name %s -map2 %s/input.map2 %s/output.aig",
modname.c_str(), tmpdir.c_str(), tmpdir.c_str()));
if (!help_mode && mod->has_attribute(ID(abc9_script))) {
if (script_save.empty())
active_design->scratchpad_unset("abc9.script");
else
active_design->scratchpad_set_string("abc9.script", script_save);
}
if (!help_mode) {
active_design->selection().selected_modules.clear();
log_pop();
if (mod->get_bool_attribute(ID(abc9_deferred_box))) {
mod->set_bool_attribute(ID(abc9_deferred_box), false);
mod->set_bool_attribute(ID::abc9_box, true);
Pass::call_on_module(active_design, mod, "portarcs -draw -write");
run("abc9_ops -prep_box");
}
}
}