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199 Commits

Author SHA1 Message Date
Martin Povišer 449e3dbbd3 cxxrtl: Mask `bmux` result appropriately 2023-12-14 06:57:28 +00:00
Merry d7cb6981b5 cxxrtl: Fix value::ctlz 2023-12-13 12:21:44 +00:00
Merry ded63bedd5 cxxrtl: Fix value::sshr 2023-12-13 12:11:57 +00:00
Merry ff53f3d2b6 cxxrtl: Fix value::shl 2023-12-13 12:02:30 +00:00
Henri Nurmi 1c8e58a736 cxxrtl: Fix formating 2023-12-13 06:08:01 +00:00
Henri Nurmi 79c0bfcb22 cxxrtl: Remove unnecessary length check 2023-12-13 06:08:01 +00:00
Henri Nurmi dbff694e3d cxxrtl: Use the base name of the interface file for the include directive 
Prior to this fix, the `CxxrtlBackend` used the entire path for the include
directive when a separated interface file is generated (via the `-header`
option). This commit updates the code to use the base name of the interface
file.

Since the C++11 standard is used by default, we cannot take advantage of
the `std::filesystem` to get the basename.
 2023-12-13 06:08:01 +00:00
Martin Povišer 18d1907fa8 cxxrtl: Assert well-formedness of input to `udivmod` 2023-12-12 10:08:12 +01:00
Martin Povišer 6206a3af30 cxxrtl: Handle case of `Bits < 4` in formatting of values 2023-12-12 09:51:17 +01:00
Martin Povišer c848d98d91 cxxrtl: Fix `udivmod` logic 2023-12-11 22:11:35 +01:00
Martin Povišer bcf5e92389 cxxrtl: Fix `ctlz` implementation 2023-12-11 22:10:51 +01:00
Merry 0681baae19 cxxrtl: Extract divmod algorithm into value 2023-12-09 19:23:04 +00:00
Merry 99c8143ded cxxrtl: Remove redundant divmod 2023-12-09 19:23:04 +00:00
Catherine 62bbd086b1 cxxrtl: reorganize runtime component files. 
In preparation for substantial expansion of CXXRTL's runtime, this commit
reorganizes the files used by the implementation. Only minimal changes are
required in a consumer.

First, change:
  -I$(yosys-config --datdir)/include
to:
  -I$(yosys-config --datdir)/include/backends/cxxrtl/runtime

Second, change:
  #include <backends/cxxrtl/cxxrtl.h>
to:
  #include <cxxrtl/cxxrtl.h>
(and do the same for cxxrtl_vcd.h, etc.)
 2023-11-28 15:32:36 +00:00
Catherine 6ffc315936 cxxrtl: export wire attributes through the C API. 
Co-authored-by: Charlotte <charlotte@lottia.net>
 2023-10-25 16:01:48 +00:00
Asherah Connor 4a475fa7a2 cxxrtl: include iostream when prints are used 2023-08-17 07:08:22 +02:00
Charlotte 2829cd9caa cxxrtl_backend: move sync $print grouping out of dump into analyze 2023-08-11 04:46:52 +02:00
Charlotte ce245b5105 cxxrtl_backend: respect sync `$print` priority 
We add a new flow graph node type, PRINT_SYNC, as they don't get handled
with regular CELL_EVALs.  We could probably move this grouping out of
the dump method.
 2023-08-11 04:46:52 +02:00
Charlotte 4ffdee65e0 cxxrtl: store comb $print cell last EN/ARGS in module 
statics were obviously wrong -- may be multiple instantiations of any
given module.  Extend test to cover this.
 2023-08-11 04:46:52 +02:00
Charlotte 843ad9331b cxxrtl: WIP: adjust comb display cells to only fire on change 
Naming and use of statics to be possibly revised.
 2023-08-11 04:46:52 +02:00
Charlotte 7f7c61c9f0 fmt: remove lzero by lowering during Verilog parse 
See https://github.com/YosysHQ/yosys/pull/3721#issuecomment-1502037466
-- this reduces logic within the cell, and makes the rules that apply
much more clear.
 2023-08-11 04:46:52 +02:00
Charlotte fc0acd0ad1 cxxrtl: restrict -print-output to cout, cerr 2023-08-11 04:46:52 +02:00
Charlotte f9b149fa7b cxxrtl: add "-print-output" option, test in fmt 2023-08-11 04:46:52 +02:00
Charlotte bfa8b631bf cxxrtl: remove unused signedDivideWithRemainder 2023-08-11 04:46:52 +02:00
Charlotte 3571bf2c2d fmt: fuzz, remove some unnecessary busywork 
Removing some signed checks and logic where we've already guaranteed the
values to be positive.  Indeed, in these cases, if a negative value got
through (per my realisation in the signed fuzz harness), it would cause
an infinite loop due to flooring division.
 2023-08-11 04:46:52 +02:00
Charlotte 2ae551c0af fmt: fuzz, fix (remove extraneous + incorrect fill) 
"blk + chunks" is often an overrun, plus the fill is unnecessary; we
throw blk away immediately.
 2023-08-11 04:46:52 +02:00
Charlotte c382d7d3ac fmt: %t/$time support 2023-08-11 04:46:52 +02:00
Charlotte 52dc397a50 cxxrtl: don't use signed divide with unsigned/pos values 
Incorrect for unsigned, wasted effort for positive signed.
 2023-08-11 04:46:52 +02:00
Charlotte 095b093f4a cxxrtl: first pass of $print impl 2023-08-11 04:46:52 +02:00
Charlotte eb397592f0 cxxrtl: add `$divfloor`. 2023-06-28 15:27:06 +01:00
Michael Nolan 24b895778a Add support for GHDL modfloor operator 2022-07-05 15:15:54 -04:00
Marcelina Kościelnicka 93508d58da Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
Catherine fc049e84a9 cxxrtl: don't reset elided wires with \init attribute. 2021-12-25 01:06:10 +00:00
Catherine 7f2ea7d222 cxxrtl: demote wires not inlinable only in debug_eval to locals. 
Fixes #3112.

Co-authored-by: Irides <irides@irides.network>
 2021-12-15 09:14:33 +00:00
Catherine 55c9fb3b18 cxxrtl: preserve interior memory pointers across reset. 
Before this commit, values, wires, and memories with an initializer
were value-initialized in emitted C++ code. After this commit, all
values, wires, and memories are default-initialized, and the default
constructor of generated modules calls the reset() method, which
assigns the members that have an initializer.
 2021-12-11 16:40:06 +00:00
whitequark 7c9e498662 cxxrtl: use unique_ptr<value<>[]> to store memory contents. 
This makes the depth properly immutable.
 2021-12-11 14:52:37 +00:00
Marcelina Kościelnicka e7d89e653c Hook up $aldff support in various passes. 2021-10-02 21:01:21 +02:00
Marcelina Kościelnicka e6f3d1c225 kernel/mem: Introduce transparency masks. 2021-08-11 00:04:16 +02:00
whitequark a04844bdf8
Merge pull request #2885 from whitequark/cxxrtl-fix-2883 
cxxrtl: treat wires with multiple defs as not inlinable
 2021-07-20 13:12:11 +00:00
whitequark 1a6ddf7892 cxxrtl: treat wires with multiple defs as not inlinable. 
Fixes #2883.
 2021-07-20 10:30:39 +00:00
whitequark 225af830c1 cxxrtl: treat assignable internal wires used only for debug as locals. 
This issue was introduced in commit 4aa65f40 while fixing #2739.

Fixes #2882.
 2021-07-20 10:10:42 +00:00
whitequark fc84f23001 cxxrtl: escape colon in variable names in VCD writer. 
The following VCD file crashes GTKWave's VCD loader:

    $var wire 1 ! x:1 $end
    $enddefinitions $end

In practice, a colon can be a part of a variable name that is
translated from a Verilog function, something like:

    update$func$.../hdl/hazard3_csr.v:350$2534.$result
 2021-07-19 16:22:55 +00:00
whitequark 948fc10d7b cxxrtl: add debug_item::{get,set}. 
Fixes #2877.
 2021-07-18 06:20:45 +00:00
whitequark 4aa65f406f cxxrtl: treat internal wires used only for debug as constants. 
Fixes #2739 (again).
 2021-07-17 14:23:57 +00:00
whitequark 2db4137514
Merge pull request #2874 from whitequark/cxxrtl-fix-2589 
cxxrtl: run hierarchy pass regardless of (*top*) attribute presence
 2021-07-16 11:12:19 +00:00
whitequark efc43270fa
Merge pull request #2873 from whitequark/cxxrtl-fix-2500 
cxxrtl: emit debug items for unused public wires
 2021-07-16 11:01:10 +00:00
whitequark 5b003d6e5c cxxrtl: run hierarchy pass regardless of (*top*) attribute presence. 
The hierarchy pass does a lot more than just finding the top module,
mainly resolving implicit (positional, wildcard) module connections.

Fixes #2589.
 2021-07-16 10:27:47 +00:00
whitequark 09218896d6 cxxrtl: emit debug items for unused public wires. 
This greatly improves debug information coverage.

Fixes #2500.
 2021-07-16 10:14:40 +00:00
whitequark b28ca7f5ac cxxrtl: don't expect user cell inputs to be wires. 
Ports can be connected to constants, too. (Usually resets.)

Fixes #2521.
 2021-07-16 09:51:52 +00:00
whitequark 44a3d924ce cxxrtl: don't mark buffered internal wires as UNUSED for debug. 
Public wires may alias buffered internal wires, so keep BUFFERED
wires in debug information even if they are private. Debug items are
only created for public wires, so this does not otherwise affect how
debug information is emitted.

Fixes #2540.
Fixes #2841.
 2021-07-16 07:54:49 +00:00