Commit Graph

135 Commits

Author SHA1 Message Date
Miodrag Milanovic 4bc1e1d1f1 Makes sure to set initial_top when change, fixes #3462 2022-08-26 17:12:56 +02:00
Jacob Lifshay c16c028831 add hierarchy -smtcheck
like -simcheck, but allow smtlib2_module modules.
2022-06-22 20:53:10 -07:00
Miodrag Milanovic 977002b1d2 Reorder steps in -auto-top to fix synth command, fixes #3261 2022-04-05 14:02:37 +02:00
Zachary Snow e833c6a418 verilog: use derived module info to elaborate cell connections
- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change
2021-10-25 18:25:50 -07:00
Rupert Swarbrick bd16d01c0e Split out logic for reprocessing an AstModule
This will enable other features to use same core logic for replacing an
existing AstModule with a newly elaborated version.
2021-10-25 18:25:50 -07:00
Rupert Swarbrick 7a25246a7e Use new read_id_num helper function elsewhere in hierarchy.cc 2021-07-20 10:13:15 -04:00
Rupert Swarbrick 8fd6b45a3c Extract connection checking logic from expand_module in hierarchy.cc
No functional change, but pulls more logic out of the expand_module
function.
2021-07-20 10:13:15 -04:00
Rupert Swarbrick 7d50b83322 Extract missing module support in hierarchy.cc to a helper function
I think the code is now a bit easier to follow (and has lost some
levels of indentation!).

The only non-trivial change is that I removed the check for
cell->type[0] != '$' when deciding whether to complain if we couldn't
find a module. This will always be true because of the early exit
earlier in the function.
2021-07-14 22:54:50 -04:00
Rupert Swarbrick e2c9580024 Move interface expansion in hierarchy.cc into a helper class
There should be no functional change, but this splits up the control
flow across functions, using class fields to hold the state that's
being tracked. The result should be a bit easier to read.

This is part of work to add bind support, but I'm doing some
refactoring in the hierarchy pass to make the code a bit easier to
work with. The idea is that (eventually) the IFExpander object will
hold all the logic for expanding interfaces, and then other code can
do bind insertion.
2021-06-16 21:48:18 -04:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
2021-06-08 00:39:36 +02:00
Zachary Snow 0d8e5d965f Sign extend port connections where necessary
- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
  signedness information
- Resolves #1418
- Resolves #2265
2020-12-18 20:33:14 -07:00
Miodrag Milanovic 412332fdb3 Validate parameters only when they are used 2020-09-25 11:40:37 +02:00
whitequark 00e7dec7f5 Replace "ILANG" with "RTLIL" everywhere.
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
2020-08-26 17:29:32 +00:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
clairexen 0f209378a8
Merge pull request #2089 from rswarbrick/modports
Simplify a modport check in hierarchy.cc
2020-06-08 15:48:11 +02:00
Rupert Swarbrick 1158bbf7db Fix small typos in documentation for hierarchy command 2020-05-28 11:39:44 +01:00
Rupert Swarbrick 7746bba69a Simplify a modport check in hierarchy.cc
This code originally comes from commit 458a940. When an interface is
used via a modport, code in genrtlil.cc sets '\\interface_type' and
'\\interface_modport' properties on the wire.

In hierarchy.cc, we pick up the modport name and add it to a dict
called modports_used_in_submodule (that maps connection source to
modport name).

Before this patch, the modport name is retrieved as a strpool and then
iterated over in an arbitrary order, discarding all entries but the
last. In practice, the pool will always have 0 or 1 entries because
the string used to construct it is a valid identifier, so doesn't
contain any pipe symbols.

This patch changes the code to retrieve the modport name as just a
string. This will have the same effect in practice, but may be a bit
less confusing!

The code also gets moved down closer to where the result is used,
which might be a bit more efficient since we won't always get as far
as the check.

The patch also removes some commented-out code, which I think was
intended to add some typechecking at some point, but was never
implemented. Since this dates back to October 2018, I think it makes
more sense to just take it out.
2020-05-26 16:50:42 +01:00
Marcelina Kościelnicka 846c79b312 hierarchy: Convert positional parameters to named.
Fixes #1821.
2020-04-21 19:09:00 +02:00
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Eddie Hung fdafb74eb7 kernel: use more ID::* 2020-04-02 07:14:08 -07:00
Alberto Gonzalez 4c92f9380c
Fix double deletion in `passes/hierarchy/hierarchy.cc`.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-30 16:43:54 +00:00
Alberto Gonzalez b88faceced
Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`. 2020-03-19 06:49:52 +00:00
David Shah 4bfd2ef4f3 sv: Improve handling of wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah 7e741714df hierarchy: Correct handling of wildcard port connections with default values
Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
David Shah 5df591c023 hierarchy: Resolve SV wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
Eddie Hung d2306d7b1d Adopt @cliffordwolf's suggestion 2019-09-03 12:18:50 -07:00
Eddie Hung 116c249601 -auto-top should check $abstract (deferred) modules with (* top *) 2019-08-28 19:59:25 -07:00
Eddie Hung 48d0f99406 stoi -> atoi 2019-08-07 11:09:17 -07:00
Eddie Hung ee7c970367 IdString::str().substr() -> IdString::substr() 2019-08-06 19:08:33 -07:00
Eddie Hung 234fcf1724 Fix typos 2019-08-06 19:07:45 -07:00
Eddie Hung e38f40af5b Use IdString::begins_with() 2019-08-06 16:42:25 -07:00
Clifford Wolf 3da5288ce0 Use input default values in hierarchy pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 11:49:20 +02:00
Clifford Wolf ba2185ead8 Refactor hierarchy wand/wor handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-28 16:43:25 +02:00
Stefan Biereigel ed625a3102 move wand/wor resolution into hierarchy pass 2019-05-27 18:00:22 +02:00
Clifford Wolf ec39cfd0ad Add "hierarchy -chparam" support for non-verific top modules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-03 22:03:43 +02:00
Eddie Hung eb21bf3651 log_warning_noprefix -> log_warning as per review 2019-05-03 20:53:25 +02:00
Eddie Hung a27b42e975 WIP -chparam support for hierarchy when verific 2019-05-03 20:53:25 +02:00
Clifford Wolf f4abc21d8a Add "whitebox" attribute, add "read_verilog -wb"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-18 17:45:47 +02:00
Clifford Wolf ae9286386d Only run derive on blackbox modules when ports have dynamic size
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 12:36:46 -08:00
Clifford Wolf c258b99040 Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to -check
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:41:36 +01:00
Jim Lawson 71bcc4c644 Address requested changes - don't require non-$ name.
Suppress warning if name does begin with a `$`.
Fix hierachy tests so they have something to grep.
Announce hierarchy test types.
2019-02-22 16:06:10 -08:00
Jim Lawson 5c4a72c43e Fix normal (non-array) hierarchy -auto-top.
Add simple test.
2019-02-19 14:35:15 -08:00
Jim Lawson 5c504c5ae6 Define basic_cell_type() function and use it to derive the cell type for array references (instead of duplicating the code). 2019-02-15 11:31:37 -08:00
whitequark efa278e232 Fix typographical and grammatical errors and inconsistencies.
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
Ruben Undheim 436e3c0a7c Refactor code to avoid code duplication + added comments 2018-10-20 16:06:48 +02:00
Ruben Undheim 397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00
Ruben Undheim c50afc4246 Documentation improvements etc.
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
2018-10-13 20:34:44 +02:00
Ruben Undheim 458a94059e Support for 'modports' for System Verilog interfaces 2018-10-12 21:11:48 +02:00
Ruben Undheim 75009ada3c Synthesis support for SystemVerilog interfaces
This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes.
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00