yosys

Commit Graph

Author	SHA1	Message	Date
Keith Rothman	3090951d54	Changes required for VPR place and route synth_xilinx. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>	2019-03-01 12:02:27 -08:00
Clifford Wolf	6991c132b5	Add Xilinx RAM64X1D and RAM128X1D simulation models	2018-03-07 17:31:48 +01:00
Clifford Wolf	8a69759306	Add techlibs/xilinx/lut2lut.v	2017-07-10 12:09:05 +02:00
Clifford Wolf	ff5c61b120	Added black box modules for all the 7-series design elements (as listed in ug953)	2016-03-19 11:09:10 +01:00
Clifford Wolf	c475deec6c	Switched to Python 3	2015-08-22 09:59:33 +02:00
Clifford Wolf	9596fe74de	Another bugfix for ice40 and xilinx brams_init make rules	2015-08-16 21:39:34 +02:00
Clifford Wolf	aedcfd6fd3	Fixed Makefile rules for generated share files	2015-08-16 21:15:07 +02:00
Clifford Wolf	e4ef000b70	Adjust makefiles to work with out-of-tree builds This is based on work done by Larry Doolittle	2015-08-12 15:04:44 +02:00
Clifford Wolf	61512b6f41	Verific build fixes	2015-05-17 08:19:52 +02:00
Clifford Wolf	b00cad81d7	Towards DRAM support in Xilinx flow	2015-04-09 08:17:14 +02:00
Clifford Wolf	8520b7fbe0	Added support for initialized xilinx brams	2015-04-06 17:07:10 +02:00
Clifford Wolf	4389d9306e	Added Xilinx bram black-box modules	2015-04-06 08:44:30 +02:00
Clifford Wolf	d29d26f882	Various cleanups in xilinx techlib	2015-01-18 19:43:54 +01:00
Clifford Wolf	7031231145	Added MUXCY and XORCY support to synth_xilinx	2015-01-17 15:39:54 +01:00
Clifford Wolf	1d96277f5d	Added add_share_file Makefile macro	2015-01-08 00:23:18 +01:00
Clifford Wolf	8898897f7b	Towards Xilinx bram support	2015-01-04 14:23:30 +01:00
Clifford Wolf	b17d6531c8	Added "make PRETTY=1"	2014-07-24 17:15:01 +02:00
Clifford Wolf	4a3669d871	Added synth_xilinx command	2013-10-27 09:51:06 +01:00

18 Commits