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4126 Commits

Author SHA1 Message Date
Clifford Wolf 9228f015a3 Update ABC to git rev 2ddc57d 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 17:22:28 +01:00
Clifford Wolf 82aaf6d908 Add "write_aiger -I -O -B" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-12 09:27:33 +01:00
Clifford Wolf ef1c61aae4 Merge branch 'master' of github.com:YosysHQ/yosys 2018-11-12 09:10:25 +01:00
Clifford Wolf dbc4cb8f4a
Merge pull request #697 from eddiehung/xilinx_ps7 
Add support for PS7 block for Xilinx
 2018-11-12 09:09:22 +01:00
Clifford Wolf 317cc9c2b7
Merge pull request #695 from daveshah1/ecp5_bb 
ecp5: Adding some blackbox cells
 2018-11-12 09:08:49 +01:00
Clifford Wolf d1372873e8 Update ABC to git rev 68da3cf 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-11 19:37:31 +01:00
Eddie Hung 99a14b0e37 Add support for Xilinx PS7 block 2018-11-10 12:45:07 -08:00
Clifford Wolf 5387ccb041 Set Verific flag vhdl_support_variable_slice=1 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-09 21:03:23 +01:00
David Shah fae3e645a2 ecp5: Add 'fake' DCU parameters 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-09 18:25:42 +00:00
David Shah 960c8794fa ecp5: Add blackboxes for ancillary DCU cells 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-09 15:18:30 +00:00
Clifford Wolf 43ee1f3f62
Merge pull request #696 from arjenroodselaar/verific_darwin 
Use appropriate static libraries when building with Verific on MacOS
 2018-11-09 13:02:49 +01:00
Clifford Wolf 05d2e5d773 Fix "make ystests" to use correct Yosys binary 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-08 09:58:47 +01:00
Arjen Roodselaar 4e846694f7 Use appropriate static libraries when building with Verific on MacOS 2018-11-07 23:18:47 -08:00
Clifford Wolf 825b4c1aa9
Merge pull request #693 from YosysHQ/rlimit 
improve rlimit handling in smtio.py
 2018-11-07 20:16:40 +01:00
David Shah 1f51332808 ecp5: Adding some blackbox cells 
Signed-off-by: David Shah <dave@ds0.me>
 2018-11-07 14:56:38 +00:00
Clifford Wolf b54bf7c0f9 Limit stack size to 16 MB on Darwin 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-07 15:32:34 +01:00
Clifford Wolf 7bd2144d03
Merge pull request #694 from trcwm/dffmap_expr_fix 
DFFLIBMAP: changed 'missing pin' error into a warning.
 2018-11-06 12:21:05 +01:00
Niels Moseley cfc9b9147c DFFLIBMAP: changed 'missing pin' error into a warning with additional reason/info. 2018-11-06 12:11:52 +01:00
Clifford Wolf f6c4485a3a Run solver in non-incremental mode whem smtio.py is configured for non-incremental solving 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-06 11:11:05 +01:00
Clifford Wolf 60ecc5c70c Update ABC rev to 4d56acf 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-06 11:10:27 +01:00
Clifford Wolf 4c50e3abb9 Fix for improved smtio.py rlimit code 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-06 10:09:03 +01:00
Clifford Wolf 79075d123f Improve stack rlimit code in smtio.py 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-06 10:05:23 +01:00
Clifford Wolf 719e29404a Allow square brackets in liberty identifiers 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-05 12:33:33 +01:00
Clifford Wolf 8f50f289b9
Merge pull request #691 from arjenroodselaar/stacksize 
Use conservative stack size for SMT2 on MacOS
 2018-11-05 09:19:56 +01:00
Arjen Roodselaar 2b93542171 Use conservative stack size for SMT2 on MacOS 2018-11-04 21:58:09 -08:00
Clifford Wolf 36ea98385f Add warning for SV "restrict" without "property" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-04 15:57:17 +01:00
Clifford Wolf d0acea4f2e Add proper error message for when smtbmc "append" fails 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-04 14:41:28 +01:00
Clifford Wolf 64e0582c29 Various indenting fixes in AST front-end (mostly space vs tab issues) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-04 10:19:32 +01:00
Clifford Wolf 68304c6d17
Merge pull request #687 from trcwm/master 
Liberty file: error when it contains pin references to non-existing pins
 2018-11-04 10:08:33 +01:00
Clifford Wolf 18a4c1cdac
Merge pull request #688 from ZipCPU/rosenfell 
Make rose and fell dependent upon LSB only
 2018-11-04 10:04:48 +01:00
ZipCPU 39f891aebc Make and dependent upon LSB only 2018-11-03 13:39:32 -04:00
Niels Moseley 04cd179696 Liberty file newline handling is more relaxed. More descriptive error message 2018-11-03 18:38:49 +01:00
Niels Moseley d1e8249f9a Report an error when a liberty file contains pin references that reference non-existing pins 2018-11-03 18:07:51 +01:00
Clifford Wolf d86ea6badd Do not generate "reg assigned in a continuous assignment" warnings for "rand reg" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-01 15:25:24 +01:00
Clifford Wolf b6781c6f4b Add support for signed $shift/$shiftx in smt2 back-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-01 11:40:58 +01:00
Clifford Wolf b4d82aa245 Merge branch 'igloo2' 2018-10-31 15:37:39 +01:00
Clifford Wolf d084fb4c3f Fix sf2 LUT interface 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-31 15:36:53 +01:00
Clifford Wolf cf79fd4376 Basic SmartFusion2 and IGLOO2 synthesis support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-31 15:28:57 +01:00
Clifford Wolf 82965d60f5
Merge pull request #680 from jburgess777/fix-empty-string-back-assert 
Avoid assert when label is an empty string
 2018-10-30 11:25:07 +01:00
Jon Burgess 6732e56632 Avoid assert when label is an empty string 
Calling back() on an empty string is not allowed and triggers
an assert with recent gcc:

$ cd manual/PRESENTATION_Intro
$ ../../yosys counter.ys
...
/usr/include/c++/8/bits/basic_string.h:1136: std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::back() [with _CharT = char; _Traits = std::char_traits<char>; _Alloc = std::allocator<char>; std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference = char&]: Assertion '!empty()' failed.

802             if (label.back() == ':' && GetSize(label) > 1)
(gdb) p label
$1 = ""
 2018-10-28 14:57:04 +00:00
Clifford Wolf db676957a0
Merge pull request #678 from whentze/master 
Fix unhandled std::out_of_range in run_frontend() due to integer underflow
 2018-10-25 13:23:26 +02:00
Clifford Wolf 5ab58d4930 Fix minor typo in error message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-25 13:20:00 +02:00
Clifford Wolf 6cd5b8b76b
Merge pull request #679 from udif/pr_syntax_error 
More meaningful SystemVerilog/Verilog parser error messages
 2018-10-25 13:18:59 +02:00
Udi Finkelstein 536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
 2018-10-25 02:37:56 +03:00
Clifford Wolf 7703be045a
Merge pull request #677 from daveshah1/ecp5_dsp 
ecp5: Add blackboxes for MULT18X18D and ALU54B
 2018-10-23 19:18:45 +02:00
whentze 9ed77f5ba8 fix unhandled std::out_of_range when calling yosys with 3-character argument 2018-10-22 19:40:22 +02:00
David Shah b65932edc4 ecp5: Remove DSP parameters that don't work 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-22 16:20:38 +01:00
David Shah 101f5234ff ecp5: Add DSP blackboxes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-21 19:27:02 +01:00
Clifford Wolf 23b69ca32b Improve read_verilog range out of bounds warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-20 23:48:53 +02:00
Clifford Wolf f3de732fb4
Merge pull request #674 from rubund/feature/svinterface_at_top 
Support for SystemVerilog interfaces as ports in the top level module + test case
 2018-10-20 23:28:09 +02:00