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yosys
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3,366 Commits 75 Branches 48 Tags 61 MiB
Commit Graph

64 Commits

Author SHA1 Message Date
Clifford Wolf 05cdd58c8d Add $_ANDNOT_ and $_ORNOT_ gates 2017-05-17 09:08:29 +02:00
Clifford Wolf 5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Clifford Wolf e6d56d23b5 Fix eval implementation of $_NOR_ 2017-02-16 12:17:03 +01:00
Clifford Wolf 3928482a3c Add $cover cell type and SVA cover() support 2017-02-04 14:14:26 +01:00
Clifford Wolf bdc316db50 Added $anyseq cell type 2016-10-14 15:24:03 +02:00
Clifford Wolf 8ebba8a35f Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00
Clifford Wolf 6f41e5277d Removed $aconst cell type 2016-08-30 19:09:56 +02:00
Clifford Wolf eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf 4056312987 Added $anyconst and $aconst 2016-07-27 15:41:22 +02:00
Clifford Wolf 5c166e76e5 Added $initstate cell type and vlog function 2016-07-21 14:23:22 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Clifford Wolf 95757efb25 Improved support for $sop cells 2016-06-17 16:31:16 +02:00
Clifford Wolf 52bb1b968d Added $sop cell type and "abc -sop" 2016-06-17 13:50:09 +02:00
Clifford Wolf 924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00
Clifford Wolf ff50bc2ac3 Added $tribuf and $_TBUF_ cell types 2015-08-16 12:54:52 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 706631225e Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types 2015-04-05 09:45:14 +02:00
Clifford Wolf b005eedf36 Added $assume cell type 2015-02-26 18:04:10 +01:00
Clifford Wolf 910556560f Added $meminit cell type 2015-02-14 10:23:03 +01:00
Clifford Wolf e13a45ae61 Added $equiv cell type 2015-01-19 11:55:05 +01:00
Clifford Wolf 0bb6b24c11 Added global yosys_celltypes 2014-12-29 14:30:33 +01:00
Clifford Wolf 137f35373f Changed more code to dict<> and pool<> 2014-12-28 19:24:24 +01:00
Clifford Wolf 032511fac8 Added functionality to dff2dffe pass 2014-12-08 15:38:58 +01:00
Clifford Wolf fad9cec47b Added $_DFFE_??_ cell types 2014-12-08 10:43:38 +01:00
Clifford Wolf 4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf c3e779a65f Added $_BUF_ cell type 2014-10-03 10:12:28 +02:00
Clifford Wolf af0c8873bb Added $lcu cell type 2014-09-08 13:31:04 +02:00
Clifford Wolf d46bac3305 Added "$fa" cell type 2014-09-08 12:15:39 +02:00
Clifford Wolf b847ec8a0b Added $macc cell type 2014-09-06 15:47:46 +02:00
Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
Clifford Wolf a1c7d4a8e2 Added eval model for $lut cells 2014-08-31 17:43:31 +02:00
Clifford Wolf 4724d94fbc Added $alu cell type 2014-08-30 18:59:05 +02:00
Clifford Wolf 98442e019d Added emscripten (emcc) support to build system and some build fixes 2014-08-22 16:20:22 +02:00
Clifford Wolf 47c2637a96 Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ 2014-08-16 18:29:39 +02:00
Clifford Wolf 56a30cf42c Added CellTypes::cell_evaluable() 2014-08-16 16:17:07 +02:00
Clifford Wolf b64b38eea2 Renamed $lut ports to follow A-Y naming scheme 2014-08-15 14:18:40 +02:00
Clifford Wolf f092b50148 Renamed $_INV_ cell type to $_NOT_ 2014-08-15 14:11:40 +02:00
Clifford Wolf 1bf7a18fec Added module->ports 2014-08-14 16:22:52 +02:00
Clifford Wolf 746aac540b Refactoring of CellType class 2014-08-14 15:46:51 +02:00
Clifford Wolf 13f2f36884 RIP $safe_pmux 2014-08-14 11:39:46 +02:00
Clifford Wolf 14412e6c95 Preparations for RTLIL::IdString redesign: cleanup of existing code 2014-08-02 00:45:25 +02:00
Clifford Wolf 397b00252d Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
Clifford Wolf 7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf d4a1b0af5b Added support for dlatchsr cells 2014-03-31 14:14:40 +02:00
Clifford Wolf 9e99984336 Fixed const folding of $bu0 cells 2014-02-27 04:09:32 +01:00
Clifford Wolf d85a6bf5d3 Added $slice and $concat to CellTypes list 2014-02-07 19:50:44 +01:00
Clifford Wolf fc3b3c4ec3 Added $slice and $concat cell types 2014-02-07 17:44:57 +01:00