Clifford Wolf
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0bc95f1e04
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Added "yosys -D" feature
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2016-04-21 23:28:37 +02:00 |
Clifford Wolf
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84bf862f7c
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Spell check (by Larry Doolittle)
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2015-08-14 10:56:05 +02:00 |
Clifford Wolf
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6c84341f22
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Fixed trailing whitespaces
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2015-07-02 11:14:30 +02:00 |
Clifford Wolf
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a8f4a099b5
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Using design->selected_modules() in opt_*
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2015-02-03 23:45:01 +01:00 |
Clifford Wolf
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445686cba3
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using dict and pool in opt_reduce
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2014-12-28 21:27:05 +01:00 |
Clifford Wolf
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ab28491f27
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Added "opt -full" alias for all more aggressive optimizations
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2014-10-31 03:36:51 +01:00 |
Clifford Wolf
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f9a307a50b
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namespace Yosys
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2014-09-27 16:17:53 +02:00 |
Clifford Wolf
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2a1b08aeb3
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Added design->scratchpad
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2014-08-30 19:37:12 +02:00 |
Clifford Wolf
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13f2f36884
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RIP $safe_pmux
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2014-08-14 11:39:46 +02:00 |
Clifford Wolf
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8fd1c269ac
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Fixed a performance bug in opt_reduce
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2014-08-02 15:12:16 +02:00 |
Clifford Wolf
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bd74ed7da4
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Replaced sha1 implementation
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2014-08-01 19:01:10 +02:00 |
Clifford Wolf
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cdae8abe16
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Renamed port access function on RTLIL::Cell, added param access functions
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2014-07-31 16:38:54 +02:00 |
Clifford Wolf
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7bd2d1064f
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Using log_assert() instead of assert()
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2014-07-28 11:27:48 +02:00 |
Clifford Wolf
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10e5791c5e
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Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
Clifford Wolf
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4c4b602156
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Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-27 01:51:45 +02:00 |
Clifford Wolf
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f8fdc47d33
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Manual fixes for new cell connections API
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2014-07-26 15:58:23 +02:00 |
Clifford Wolf
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b7dda72302
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Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
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2014-07-26 15:58:23 +02:00 |
Clifford Wolf
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cc4f10883b
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Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-26 11:58:03 +02:00 |
Clifford Wolf
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2bec47a404
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Use only module->addCell() and module->remove() to create and delete cells
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2014-07-25 17:56:19 +02:00 |
Clifford Wolf
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0520bfea89
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Fixed memory corruption in "opt_reduce" pass
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2014-07-25 12:49:51 +02:00 |
Clifford Wolf
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a62c21c9c6
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Removed RTLIL::SigSpec::expand() method
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2014-07-23 19:34:51 +02:00 |
Clifford Wolf
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4b4048bc5f
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SigSpec refactoring: using the accessor functions everywhere
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2014-07-22 20:39:37 +02:00 |
Clifford Wolf
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a233762a81
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SigSpec refactoring: renamed chunks and width to __chunks and __width
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2014-07-22 20:39:37 +02:00 |
Clifford Wolf
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1241a9fd50
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Added "opt_const -fine" and "opt_reduce -fine"
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2014-07-21 16:34:16 +02:00 |
Clifford Wolf
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309ae98246
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Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port
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2014-07-18 10:28:45 +02:00 |
Clifford Wolf
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1b00861d0a
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Improved opt_reduce handling of mem wr_en mux bits
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2014-07-17 12:12:04 +02:00 |
Clifford Wolf
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d678b6533d
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improved opt_reduce for $mem/$memwr WR_EN multiplexers
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2014-07-16 14:08:51 +02:00 |
Clifford Wolf
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68c059565a
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Fixed bug in opt_reduce (see vloghammer issue_044)
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2014-05-12 12:45:47 +02:00 |
Clifford Wolf
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9b9c3327cc
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Fixed undef handling in opt_reduce
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2014-03-06 14:18:34 +01:00 |
Clifford Wolf
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e5b974fa2a
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Cleanups and bugfixes in response to new internal cell checker
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2013-11-11 00:39:45 +01:00 |
Clifford Wolf
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36954471a6
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Added help messages for opt_* passes
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2013-03-01 09:01:49 +01:00 |
Clifford Wolf
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a321a5c412
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Moved stand-alone libs to libs/ directory and added libs/subcircuit
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2013-02-27 09:32:19 +01:00 |
Clifford Wolf
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7764d0ba1d
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initial import
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2013-01-05 11:13:26 +01:00 |