riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
12,067 Commits 75 Branches 48 Tags 61 MiB
Commit Graph

12067 Commits

Author SHA1 Message Date
Martin Povišer 8b1f5fba62 passes: show: Simplify wire bit range logic 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer ad149cc42a passes: show: Factor out 'join_label_pieces' 
In two places, we are joining label pieces by a '|' separator. We go
about it by putting the separator behind each entry, then removing the
trailing separator in a final fixup pass on the built string. For easier
reading, replace those occurrences by a new factored-out
'join_label_pieces' function.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer 5848790835 passes: show: Label signed_suffix flag 
To make it easier to follow what's going on.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer 13700e12e5 passes: show: s/idx/dot_idx/ for readability 
Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
Martin Povišer e3709ce776 passes: show: Fix portbox bit ranges in case of driven signals 
When the 'show' pass generates portboxes to detail the connection of
cell ports to wires, it has special handling of signal chunk
repetitions, but those repetitions are not accounted for in the
displayed bit range in case of cell outputs. Fix that, and so bring it
into consistence with the behavior on cell inputs.

So, taking for example the following Verilog snippet,

  module DRIVER (Q);
     output [7:0] Q;
     assign Q = 8'b10101010;
  endmodule

  module main;
     wire w;
     DRIVER driver(.Q({8{w}}));
  endmodule

make the show pass display '7:0 - 8x 0:0' in the driver-to-w portbox
instead of '7:7 - 8x 0:0' which it displayed formerly.

Signed-off-by: Martin Povišer <povik@cutebit.org>
 2023-01-13 19:57:24 +01:00
github-actions[bot] 956c4e485a Bump version 2023-01-12 01:17:55 +00:00
N. Engelhardt 692a0fa33b print filename in liberty log_header 2023-01-11 21:31:46 +01:00
N. Engelhardt 4173daa708
Merge pull request #3605 from gadfort/stat-json-area 2023-01-11 16:41:44 +01:00
Claire Xen 2e3c08adc4
Merge pull request #3570 from YosysHQ/claire/eqystuff 
Various Changes for EQY
 2023-01-11 16:37:52 +01:00
Claire Xen 843f329b96
Merge branch 'master' into claire/eqystuff 2023-01-11 16:33:08 +01:00
Jannis Harder 5abaa59080
Merge pull request #3537 from jix/xprop 
New xprop pass
 2023-01-11 16:26:04 +01:00
N. Engelhardt d742d063d4 remove template declaration that stops function from being used 2023-01-11 16:09:05 +01:00
N. Engelhardt 41ce00e82a
Merge pull request #3620 from YosysHQ/gcc48_remove 2023-01-11 16:05:56 +01:00
Miodrag Milanovic 4fc5207b1e Add deprecation info to changelog 2023-01-11 11:23:23 +01:00
Miodrag Milanovic 5801152779 Deprecate gcc-4.8 2023-01-11 09:54:19 +01:00
Claire Xenia Wolf 6d56d4ecfc Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuff 2023-01-11 04:10:12 +01:00
github-actions[bot] 7b476996df Bump version 2023-01-11 01:16:47 +00:00
Miodrag Milanović 2677569d48
Merge pull request #3616 from YosysHQ/register_error 
Display error instead of assertion when pass exists
 2023-01-10 11:38:57 +01:00
Miodrag Milanović 2b622258a2
Merge pull request #3615 from YosysHQ/qbfsat_cvc5 
qbfsat support for cvc5, fixes #3608
 2023-01-10 11:38:16 +01:00
Miodrag Milanovic 40282576b0 Display error instead of assertion when pass exists 2023-01-09 17:02:56 +01:00
Miodrag Milanovic e3c0fd8b10 qbfsat support for cvc5, fixes #3608 2023-01-09 16:14:01 +01:00
github-actions[bot] f2c689403a Bump version 2023-01-05 00:16:46 +00:00
gatecat 7bac1920b2 nexus: Fix BRAM write enable in PDP mode 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-04 17:59:36 +01:00
github-actions[bot] d3216593da Bump version 2023-01-04 00:16:03 +00:00
Miodrag Milanovic c34d308bbd Next dev cycle 2023-01-03 09:36:13 +01:00
Miodrag Milanovic e02b7f64bc Release version 0.25 2023-01-03 09:34:45 +01:00
github-actions[bot] a27a297ebc Bump version 2023-01-03 00:15:41 +00:00
Peter Gadfort 7971154e72 Merge branch 'master' into stat-json-area 2023-01-02 12:46:41 -05:00
Miodrag Milanović 583ab81670
Merge pull request #3606 from YosysHQ/fix_vs 
Remove cache
 2023-01-02 17:47:13 +01:00
Miodrag Milanovic a935752df6 Remove cache 2023-01-02 17:16:51 +01:00
N. Engelhardt fcd1c68ab7 add note to help about how to chain commands 2023-01-02 16:10:28 +01:00
Miodrag Milanović 257b41cd1f
Merge pull request #3577 from KrystalDelusion/deprecate_manual 
Deprecate manual
 2023-01-02 16:07:36 +01:00
Peter Gadfort 58cca9592d stat: ensure area is included in json output 
Signed-off-by: Peter Gadfort <peter.gadfort@gmail.com>
 2022-12-29 21:51:46 -05:00
Claire Xenia Wolf 029b0aac7f Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuff 2022-12-21 14:50:23 +01:00
Claire Xenia Wolf 1bc832a8e1 Allow non-unique modules without state in sim writeback-mode 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-21 10:43:02 +01:00
Claire Xenia Wolf a9072dc23c Small bugfix in uniquify pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-21 10:41:48 +01:00
Jannis Harder 3ebc50dee4
Merge pull request #3467 from jix/fix_cellarray_simplify 
simplify: Do not recursively simplify AST_CELL within AST_CELLARRAY
 2022-12-19 16:05:13 +01:00
KrystalDelusion f2a4e5f1a0 Fixing other references to the manual 
And files that were in the directory.
 2022-12-19 10:42:21 +13:00
KrystalDelusion f33a21eea4 Removed manual from make clean 2022-12-19 10:10:34 +13:00
KrystalDelusion aeb40d4ddf Remove make targets for manual 
Leaves the clean, since presentation source is still directly buildable and cleanable.
 2022-12-19 10:08:40 +13:00
github-actions[bot] 69cbef9666 Bump version 2022-12-16 00:16:00 +00:00
Miodrag Milanović 76de4455e6
Merge pull request #3588 from YosysHQ/noblackbox 
respect noblackbox attribute in verific
 2022-12-15 09:08:18 +01:00
Miodrag Milanovic b867dee241 respect noblackbox attribute in verific 2022-12-15 08:17:53 +01:00
github-actions[bot] 5d893c4b03 Bump version 2022-12-13 00:17:31 +00:00
Jannis Harder 4a0ed35aab xprop: Improve signal splitting code 
Avoid splitting output ports twice when combining -split-outputs with
-split-public and clean up the corresponding code.
 2022-12-12 17:51:01 +01:00
Jannis Harder 2093cf07e4
Merge pull request #3581 from jix/formalff-error 
formalff: Proper error messages on async inputs for the -clk2ff mode
 2022-12-12 16:39:10 +01:00
Claire Xenia Wolf 6a6e1d8424 Improvements in "viz" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-09 18:28:17 +01:00
Jannis Harder 967529abb1 formalff: Proper error messages on async inputs for the -clk2ff mode 2022-12-09 15:25:40 +01:00
Claire Xenia Wolf dc14def5f3 Add gold-x handing to miter cross port handling 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-08 22:14:16 +01:00
Claire Xenia Wolf 3454bddbe2 Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuff 2022-12-08 20:06:23 +01:00