riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
5,371 Commits 92 Branches 49 Tags 39 MiB
Commit Graph

12 Commits

Author SHA1 Message Date
Eddie Hung ae89e6ab26 Add whitebox support to DRAM 2019-05-23 08:58:57 -07:00
Eddie Hung 13ad19482f Merge remote-tracking branch 'origin' into xc7srl 2019-04-20 10:41:43 -07:00
Keith Rothman 1f9235ede5 Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-12 09:35:15 -07:00
Eddie Hung ff385a5ad0 Remove duplicate STARTUPE2 2019-04-03 08:14:09 -07:00
Eddie Hung 46753cf89f Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-22 13:10:42 -07:00
David Shah 46f6a60d58 xilinx: Add keep attribute where appropriate 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 13:57:17 +00:00
Eddie Hung f1a8e8a480 Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-14 08:59:19 -07:00
Keith Rothman 3090951d54 Changes required for VPR place and route synth_xilinx. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 12:02:27 -08:00
Eddie Hung 1da0909662 Remove SRL16/32 from cells_xtra 2019-02-28 13:56:45 -08:00
Eddie Hung 99a14b0e37 Add support for Xilinx PS7 block 2018-11-10 12:45:07 -08:00
Clifford Wolf 5f1fea08d5 Add inout ports to cells_xtra.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-04 11:30:55 +02:00
Clifford Wolf ff5c61b120 Added black box modules for all the 7-series design elements (as listed in ug953) 2016-03-19 11:09:10 +01:00