Clifford Wolf
|
5b3dc07b9a
|
Removed old "constmap" from wreduce code
|
2014-08-05 16:53:53 +02:00 |
Clifford Wolf
|
523df73145
|
Added support for truncating of wires to wreduce pass
|
2014-08-05 14:47:03 +02:00 |
Clifford Wolf
|
d3b1a29708
|
Cleanups and improvements in wreduce pass
|
2014-08-05 13:11:04 +02:00 |
Clifford Wolf
|
1c182cedb7
|
Added mux support to wreduce command
|
2014-08-05 12:49:53 +02:00 |
Clifford Wolf
|
91dd87e60b
|
Improved scope resolution of local regs in Verilog+AST frontend
|
2014-08-05 12:15:53 +02:00 |
Clifford Wolf
|
0129d41efa
|
Fixed AST handling of variables declared inside a functions main block
|
2014-08-05 08:35:51 +02:00 |
Clifford Wolf
|
0bb6942218
|
Added "show -signed"
|
2014-08-04 15:40:08 +02:00 |
Clifford Wolf
|
b5a3419ac2
|
Added support for non-standard "module mod_name(...);" syntax
|
2014-08-04 15:40:07 +02:00 |
Clifford Wolf
|
ebbbe7fc83
|
Added RTLIL::IdString::in(...)
|
2014-08-04 15:40:07 +02:00 |
Clifford Wolf
|
c7f99be3be
|
Fixed "share" for memory read ports
|
2014-08-03 20:22:33 +02:00 |
Clifford Wolf
|
358bf70a21
|
Added "wreduce" to some of the standard test benches
|
2014-08-03 20:22:33 +02:00 |
Clifford Wolf
|
027376515a
|
Progress in "wreduce" pass
|
2014-08-03 20:02:42 +02:00 |
Clifford Wolf
|
0b02f6ca30
|
Added "wreduce" command (work in progress)
|
2014-08-03 15:02:05 +02:00 |
Clifford Wolf
|
653edd7a2f
|
Added query() API to ModIndex
|
2014-08-03 15:00:38 +02:00 |
Clifford Wolf
|
75423169c5
|
Added ID() macro for static IdStrings
|
2014-08-03 14:59:13 +02:00 |
Clifford Wolf
|
014a41fcf3
|
Implemented recursive techmap
|
2014-08-03 12:40:43 +02:00 |
Clifford Wolf
|
9bb5298c10
|
Fixes in show command (related to new IdString)
|
2014-08-03 12:40:23 +02:00 |
Clifford Wolf
|
08ec33a5e5
|
Implemented simplemap support for "techmap -extern"
|
2014-08-02 21:55:13 +02:00 |
Clifford Wolf
|
bc947d4c7b
|
Fixed a va_list corruption in logv_error()
|
2014-08-02 21:54:30 +02:00 |
Clifford Wolf
|
88cf00ce78
|
Be more conservative with printing decimal numbers in verilog backend
|
2014-08-02 21:54:02 +02:00 |
Clifford Wolf
|
ca1b5d50e0
|
Improved verilog output for ordinary $mux cells
|
2014-08-02 21:10:08 +02:00 |
Clifford Wolf
|
b6acbc82e6
|
Bugfix in "techmap -extern"
|
2014-08-02 20:54:30 +02:00 |
Clifford Wolf
|
8e7361f128
|
Removed at() method from RTLIL::IdString
|
2014-08-02 19:08:02 +02:00 |
Clifford Wolf
|
04727c7e0f
|
No implicit conversion from IdString to anything else
|
2014-08-02 18:58:40 +02:00 |
Clifford Wolf
|
768eb846c4
|
More bugfixes related to new RTLIL::IdString
|
2014-08-02 18:14:21 +02:00 |
Clifford Wolf
|
08392aad8f
|
Limit size of log_signal buffer to 100 elements
|
2014-08-02 15:52:21 +02:00 |
Clifford Wolf
|
e590ffc84d
|
Improvements in new RTLIL::IdString implementation
|
2014-08-02 15:44:10 +02:00 |
Clifford Wolf
|
8fd1c269ac
|
Fixed a performance bug in opt_reduce
|
2014-08-02 15:12:16 +02:00 |
Clifford Wolf
|
60f3dc9923
|
Implemented new reference counting RTLIL::IdString
|
2014-08-02 15:11:35 +02:00 |
Clifford Wolf
|
97ad0623df
|
Fixed memory corruption related to id2cstr()
|
2014-08-02 13:34:07 +02:00 |
Clifford Wolf
|
b9bd22b8c8
|
More cleanups related to RTLIL::IdString usage
|
2014-08-02 13:19:57 +02:00 |
Clifford Wolf
|
14412e6c95
|
Preparations for RTLIL::IdString redesign: cleanup of existing code
|
2014-08-02 00:45:25 +02:00 |
Clifford Wolf
|
75ffd1643c
|
Added logfile hash to statistics footer
|
2014-08-01 19:43:28 +02:00 |
Clifford Wolf
|
bd74ed7da4
|
Replaced sha1 implementation
|
2014-08-01 19:01:10 +02:00 |
Clifford Wolf
|
1e224506be
|
Added per-pass cpu usage statistics
|
2014-08-01 18:42:10 +02:00 |
Clifford Wolf
|
d13eb7e099
|
Added ModIndex helper class, some changes to RTLIL::Monitor
|
2014-08-01 17:14:32 +02:00 |
Clifford Wolf
|
97a17d39e2
|
Packed SigBit::data and SigBit::offset in a union
|
2014-08-01 15:25:42 +02:00 |
Clifford Wolf
|
5e641acc90
|
Consolidated hana test benches into fewer files
for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;
..etc..
|
2014-08-01 03:57:37 +02:00 |
Clifford Wolf
|
03ef9a75c6
|
Added "test_autotb -n <num_iter>" option
|
2014-08-01 03:55:51 +02:00 |
Clifford Wolf
|
32a1cc3efd
|
Renamed modwalker.h to modtools.h
|
2014-07-31 23:30:18 +02:00 |
Clifford Wolf
|
62c8a71525
|
Various cleanups in Makefile, Renamed default configurations
|
2014-07-31 23:14:17 +02:00 |
Clifford Wolf
|
069fe0db42
|
Added compiler + compiler version + compiler flags to version string
|
2014-07-31 23:07:00 +02:00 |
Clifford Wolf
|
c6fd82c70b
|
Fixed build of verific bindings
|
2014-07-31 16:45:23 +02:00 |
Clifford Wolf
|
cdae8abe16
|
Renamed port access function on RTLIL::Cell, added param access functions
|
2014-07-31 16:38:54 +02:00 |
Clifford Wolf
|
b5a9e51b96
|
Added "trace" command
|
2014-07-31 15:02:16 +02:00 |
Clifford Wolf
|
cd9407404a
|
Added RTLIL::Monitor
|
2014-07-31 14:45:14 +02:00 |
Clifford Wolf
|
e6d33513a5
|
Added module->design and cell->module, wire->module pointers
|
2014-07-31 14:11:39 +02:00 |
Clifford Wolf
|
1cb25c05b3
|
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
|
2014-07-31 13:19:47 +02:00 |
Clifford Wolf
|
1202f7aa4b
|
Renamed "stdcells.v" to "techmap.v"
|
2014-07-31 02:32:00 +02:00 |
Clifford Wolf
|
6ca0c569d9
|
Added "techmap -assert"
|
2014-07-31 02:21:41 +02:00 |