riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
13,774 Commits 92 Branches 49 Tags 39 MiB
Commit Graph

13774 Commits

Author SHA1 Message Date
Krystine Sherwin a7e1c6e530
codeowners: adopting docs folder 2024-01-27 11:32:08 +13:00
Krystine Sherwin 7e524e0588
Update workflows to Node.js 20 
Node.js 16 actions are deprecated.  For more information see: https://github.blog/changelog/2023-09-22-github-actions-transitioning-from-node-16-to-node-20/.
 2024-01-27 11:20:48 +13:00
Philippe Sauter 68a9aa7c29 peepopt: handle offset too large in `shiftadd` 
If the offset is larger than the signal itself,
meaning the signal is completely shifted out,
it tried to extract a negative amount of bits from the old signal.

This RTL pattern is suspicious since it is a complicated way of
arriving at a constant value, so we warn the user.
 2024-01-26 16:44:30 +01:00
Krystine Sherwin 22808e0e3f
Docs: work on selections.rst 
Highlighting the difference between `select prod %ci` and `select prod %ci2` by
introducing `sumproud.out` using the `dump` command.

Playing around with advanced cone example code.
 2024-01-26 17:29:59 +13:00
Krystine Sherwin e2e7065590
Docs: some restructure of advanced section 
- Filling out index descriptions for `using_yosys` and `using_yosys/synthesis`.
- To discourage skipping over these index pages, the toctree in
  `using_yosys/index` is hidden and instead has inline links to the two
  subsections.
- Tidying todos.
- Moves technology mapping to `techmap_synth`, leaving the techmap by example in
  the internals section. `yosys_flows` gets split up, with the coarse-grain
  intro replaced by `synthesis/index`, the extract pass moving to
  `synthesis/extract` and model checking to `more_scripting/model_checking`.
 2024-01-26 13:08:22 +13:00
Krystine Sherwin 4582ab59da
Docs: intro to memory_libmap 2024-01-26 11:15:01 +13:00
Ethan Mahintorabi 33fe2e4613
fixes char* to string conversion issue 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-01-25 17:39:18 +00:00
Ethan Mahintorabi d2a04cca0e
write_verilog: Making sure BUF cells are converted to expressions. 
These were previously not being converted correctly leading to yosys
internal cells being written to my netlist.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-01-25 17:00:05 +00:00
Jannis Harder 7c818d30f7 sim: Bring $print trigger/sampling semantics in line with FFs 2024-01-25 16:21:03 +01:00
N. Engelhardt efe4d6dbdc SigSpec/SigChunk::extract(): assert offset/length are not out of range 2024-01-25 12:28:17 +01:00
github-actions[bot] 80511ced71 Bump version 2024-01-25 00:16:42 +00:00
Krystine Sherwin 6e38848b92
Docs: updating makefiles 2024-01-25 12:35:03 +13:00
Krystine Sherwin 62d2f89c74
Revert artifact reuse 2024-01-25 12:18:06 +13:00
Krystine Sherwin 2a14c72110
test-docs: target examples directly 2024-01-25 11:36:59 +13:00
Krystine Sherwin 4ac983e56c
test-docs: Checkout Yosys 2024-01-25 11:32:39 +13:00
Krystine Sherwin bb4d69005f
Docs: can we re-use build artifacts? 2024-01-25 10:15:43 +13:00
Krystine Sherwin 57a7532227
Docs: add test-examples target 
`test` becomes `test-macros`, with a new `test` calling both `test-*` targets.
 2024-01-25 10:15:00 +13:00
Krystine Sherwin e10d9b1fe0
Remove python dep from test-docs 2024-01-25 09:38:50 +13:00
Martin Povišer 6707db93b9
Merge pull request #4157 from whitequark/cxxrtl-fix-4144 
cxxrtl: fix typo in codegen for async set/clear
 2024-01-24 18:48:45 +01:00
Martin Povišer 08fd47e970 Test roundtripping some processes to Verilog and back 2024-01-24 16:32:25 +00:00
Catherine 9cbfad2691 write_verilog: don't emit code with dangling else related to wrong condition. 2024-01-24 16:32:25 +00:00
Catherine b841d1bcbe cxxrtl: fix typo in codegen for async set/clear. 2024-01-24 16:30:01 +00:00
github-actions[bot] 3c3788ee28 Bump version 2024-01-24 00:16:36 +00:00
Krystine Sherwin 9b820108d6
Docs: add test-docs.yml 2024-01-24 11:22:38 +13:00
Krystine Sherwin 449135a9d4
Docs: adding other macro command lists 
Also updates `macro_commands.py` to skip empty lines, and moves comment
stripping earlier in parsing.
 2024-01-24 10:29:40 +13:00
Krystine Sherwin 6c8949cacc
Docs: static opt macro list 
Also adds `docs/tests/macro_commands.py` which checks all commands in
`code_examples/macro_commands` against the current yosys build. Format similar
to `run-test.sh` files: logging the file under test and reporting errors.
 2024-01-24 09:56:00 +13:00
Gabriel Gouvine c634d59c18 Issue a warning instead of a syntax error for blif delay constraints 2024-01-23 16:25:16 +00:00
Miodrag Milanovic ddfd867d29 hardcode iverilog version so it works on forkes and in PRs 2024-01-23 17:22:56 +01:00
Krystine Sherwin 95849edbba
Docs: changes from JF 
`yosys-witness` prereq `click`.
Yosys environment vars & `yosys --help` output.
Removing Ubuntu/macOS version numbers/names.
Hide `troubleshooting` page.
 2024-01-23 17:35:06 +13:00
Krystine Sherwin e63f1f5367
Docs: merge CI fix 2024-01-23 16:39:04 +13:00
github-actions[bot] 2f9fcc2e50 Bump version 2024-01-23 00:16:43 +00:00
Miodrag Milanović 3123dac77a
Merge pull request #4148 from YosysHQ/set_iverilog 
Checkout specific iverilog version (can be master as well)
 2024-01-22 18:29:36 +01:00
Miodrag Milanovic cfcd0b5729 Checkout specific iverilog version (can be master as well) 2024-01-22 17:18:39 +01:00
Catherine 3d9e44d182 hierarchy: keep display statements, like formal assertions. 2024-01-22 10:09:22 +00:00
Martin Povišer 2c4cf2b4b8
Merge pull request #4147 from stong/fix-typo 
Fix typo in stat help
 2024-01-22 10:52:01 +01:00
Krystine Sherwin 9ec1536f1f
Docs: getting_started tidy 
Rename `show` intro and point to `/cmd/show`.
Add getting_started section overview.
 2024-01-22 11:44:43 +13:00
Krystine Sherwin 65bb0d3059
Docs: updating to current 'master' 
Pulling for #4133 and removing related TODO.
 2024-01-22 11:18:07 +13:00
Krystine Sherwin 794ad381c6
Docs: scripting_intro/show_intro 
Adds two new `show` commands to `fifo.ys` for demo purposes.
Mention referencing named selections with `@<name>`.
Also adds a note to `example_synth` to point to the show intro.
 2024-01-22 11:10:02 +13:00
Stephen Tong b3e7390c0e
Fix typo in stat help 2024-01-21 16:32:05 -05:00
github-actions[bot] 8649e30668 Bump version 2024-01-20 00:16:07 +00:00
Catherine fc5ff7a265 cxxrtl: always lazily format print messages. 
This is mostly useful for collecting coverage for the future `$check`
cell, where, depending on the flavor, formatting a message may not be
wanted even for a failed assertion.
 2024-01-19 18:55:23 +00:00
Miodrag Milanovic b11449badb Make small build links, and support verific small build 2024-01-19 16:30:35 +01:00
Catherine b74d33d1b8 fmt: rename TIME to VLOG_TIME. 
The behavior of these format specifiers is highly specific to Verilog
(`$time` and `$realtime` are only defined relative to `$timescale`)
and may not fit other languages well, if at all. If they choose to use
it, it is now clear what they are opting into.

This commit also simplifies the CXXRTL code generation for these format
specifiers.
 2024-01-19 15:12:05 +00:00
Catherine 08d7f54726 cxxrtl: move a definition around. NFC 2024-01-19 15:12:05 +00:00
Jannis Harder ac6fcb2547 write_aiger: Detect and error out on combinational loops 
Without this it will overflow the stack when loops are present.
 2024-01-19 15:36:14 +01:00
Martin Povišer cb86efa50c celledges: Add test of shift cells edge data 2024-01-19 11:14:10 +01:00
Martin Povišer 134eb15c7e celledges: Clean up shift rules 2024-01-19 11:08:31 +01:00
Miodrag Milanović 6282c1f27d
Merge pull request #4137 from yrabbit/bsram-infer 
gowin: fix the BRAM mapping.
 2024-01-19 08:45:39 +01:00
YRabbit ae991abf2e gowin: fix the BRAM mapping. 
The primitives used have been corrected and changes have been made to the set of signals.
The empirically established need to set the OCEx signal to 1 when using READ_MODE=0 is reflected.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-01-19 15:26:37 +10:00
github-actions[bot] 7580821834 Bump version 2024-01-19 00:16:38 +00:00