mirror of https://github.com/YosysHQ/yosys.git
Docs: scripting_intro/show_intro
Adds two new `show` commands to `fifo.ys` for demo purposes. Mention referencing named selections with `@<name>`. Also adds a note to `example_synth` to point to the show intro.
This commit is contained in:
Krystine Sherwin
parent
14b7c581fa
commit
794ad381c6
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@ -54,78 +54,86 @@ yosys [addr_gen]*> select -set new_cells %
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yosys [addr_gen]*> select -clear
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yosys> select -list addr_gen/t:*
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addr_gen/$add$fifo.v:20$3
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addr_gen/$eq$fifo.v:17$2
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yosys> show -format dot -prefix addr_gen_show addr_gen
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4. Generating Graphviz representation of design.
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Writing dot description to `addr_gen_show.dot'.
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Dumping module addr_gen to page 1.
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yosys> show -format dot -prefix new_cells_show -notitle @new_cells
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5. Generating Graphviz representation of design.
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Writing dot description to `new_cells_show.dot'.
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Dumping selected parts of module addr_gen to page 1.
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yosys> show -color maroon3 @new_cells -color cornflowerblue p:* -notitle -format dot -prefix addr_gen_hier
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4. Generating Graphviz representation of design.
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6. Generating Graphviz representation of design.
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Writing dot description to `addr_gen_hier.dot'.
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Dumping module addr_gen to page 1.
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yosys> proc -noopt
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5. Executing PROC pass (convert processes to netlists).
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7. Executing PROC pass (convert processes to netlists).
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yosys> proc_clean
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5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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yosys> proc_rmdead
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5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Marked 2 switch rules as full_case in process $proc$fifo.v:13$1 in module addr_gen.
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Removed a total of 0 dead cases.
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yosys> proc_prune
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5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
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7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
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Removed 0 redundant assignments.
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Promoted 1 assignment to connection.
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yosys> proc_init
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5.4. Executing PROC_INIT pass (extract init attributes).
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7.4. Executing PROC_INIT pass (extract init attributes).
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Found init rule in `\addr_gen.$proc$fifo.v:0$4'.
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Set init value: \addr = 8'00000000
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yosys> proc_arst
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5.5. Executing PROC_ARST pass (detect async resets in processes).
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7.5. Executing PROC_ARST pass (detect async resets in processes).
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Found async reset \rst in `\addr_gen.$proc$fifo.v:13$1'.
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yosys> proc_rom
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5.6. Executing PROC_ROM pass (convert switches to ROMs).
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7.6. Executing PROC_ROM pass (convert switches to ROMs).
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Converted 0 switches.
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<suppressed ~2 debug messages>
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yosys> proc_mux
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5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
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7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
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Creating decoders for process `\addr_gen.$proc$fifo.v:0$4'.
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Creating decoders for process `\addr_gen.$proc$fifo.v:13$1'.
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1/1: $0\addr[7:0]
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yosys> proc_dlatch
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5.8. Executing PROC_DLATCH pass (convert process syncs to latches).
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7.8. Executing PROC_DLATCH pass (convert process syncs to latches).
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yosys> proc_dff
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5.9. Executing PROC_DFF pass (convert process syncs to FFs).
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7.9. Executing PROC_DFF pass (convert process syncs to FFs).
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Creating register for signal `\addr_gen.\addr' using process `\addr_gen.$proc$fifo.v:13$1'.
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created $adff cell `$procdff$10' with positive edge clock and positive level reset.
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yosys> proc_memwr
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5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
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7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
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yosys> proc_clean
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5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Removing empty process `addr_gen.$proc$fifo.v:0$4'.
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Found and cleaned up 2 empty switches in `\addr_gen.$proc$fifo.v:13$1'.
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Removing empty process `addr_gen.$proc$fifo.v:13$1'.
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@ -135,13 +143,13 @@ yosys> select -set new_cells t:$mux t:*dff
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yosys> show -color maroon3 @new_cells -notitle -format dot -prefix addr_gen_proc
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6. Generating Graphviz representation of design.
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8. Generating Graphviz representation of design.
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Writing dot description to `addr_gen_proc.dot'.
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Dumping module addr_gen to page 1.
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yosys> opt_expr
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7. Executing OPT_EXPR pass (perform const folding).
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9. Executing OPT_EXPR pass (perform const folding).
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Optimizing module addr_gen.
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yosys> clean
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@ -151,7 +159,7 @@ yosys> select -set new_cells t:$eq
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yosys> show -color cornflowerblue @new_cells -notitle -format dot -prefix addr_gen_clean
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8. Generating Graphviz representation of design.
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10. Generating Graphviz representation of design.
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Writing dot description to `addr_gen_clean.dot'.
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Dumping module addr_gen to page 1.
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@ -159,7 +167,7 @@ yosys> design -reset
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yosys> read_verilog fifo.v
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9. Executing Verilog-2005 frontend: fifo.v
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11. Executing Verilog-2005 frontend: fifo.v
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Parsing Verilog input from `fifo.v' to AST representation.
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Generating RTLIL representation for module `\addr_gen'.
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Generating RTLIL representation for module `\fifo'.
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@ -167,24 +175,24 @@ Successfully finished Verilog frontend.
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yosys> hierarchy -check -top fifo
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10. Executing HIERARCHY pass (managing design hierarchy).
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12. Executing HIERARCHY pass (managing design hierarchy).
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10.1. Analyzing design hierarchy..
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12.1. Analyzing design hierarchy..
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Top module: \fifo
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Used module: \addr_gen
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Parameter \MAX_DATA = 256
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10.2. Executing AST frontend in derive mode using pre-parsed AST for module `\addr_gen'.
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12.2. Executing AST frontend in derive mode using pre-parsed AST for module `\addr_gen'.
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Parameter \MAX_DATA = 256
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Generating RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'.
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Parameter \MAX_DATA = 256
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Found cached RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'.
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10.3. Analyzing design hierarchy..
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12.3. Analyzing design hierarchy..
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Top module: \fifo
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Used module: $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000
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10.4. Analyzing design hierarchy..
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12.4. Analyzing design hierarchy..
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Top module: \fifo
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Used module: $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000
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Removing unused module `\addr_gen'.
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@ -192,16 +200,16 @@ Removed 1 unused modules.
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yosys> proc
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11. Executing PROC pass (convert processes to netlists).
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13. Executing PROC pass (convert processes to netlists).
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yosys> proc_clean
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11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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13.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Cleaned up 0 empty switches.
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yosys> proc_rmdead
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11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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13.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Marked 2 switch rules as full_case in process $proc$fifo.v:64$24 in module fifo.
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Marked 1 switch rules as full_case in process $proc$fifo.v:38$16 in module fifo.
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Marked 2 switch rules as full_case in process $proc$fifo.v:13$32 in module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.
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@ -209,13 +217,13 @@ Removed a total of 0 dead cases.
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yosys> proc_prune
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11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
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13.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
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Removed 0 redundant assignments.
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Promoted 6 assignments to connections.
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yosys> proc_init
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11.4. Executing PROC_INIT pass (extract init attributes).
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13.4. Executing PROC_INIT pass (extract init attributes).
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Found init rule in `\fifo.$proc$fifo.v:0$31'.
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Set init value: \count = 9'000000000
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Found init rule in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$35'.
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@ -223,19 +231,19 @@ Found init rule in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000
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yosys> proc_arst
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11.5. Executing PROC_ARST pass (detect async resets in processes).
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13.5. Executing PROC_ARST pass (detect async resets in processes).
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Found async reset \rst in `\fifo.$proc$fifo.v:64$24'.
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Found async reset \rst in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$32'.
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yosys> proc_rom
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11.6. Executing PROC_ROM pass (convert switches to ROMs).
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13.6. Executing PROC_ROM pass (convert switches to ROMs).
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Converted 0 switches.
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<suppressed ~5 debug messages>
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yosys> proc_mux
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11.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
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13.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
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Creating decoders for process `\fifo.$proc$fifo.v:0$31'.
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Creating decoders for process `\fifo.$proc$fifo.v:64$24'.
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1/1: $0\count[8:0]
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@ -249,11 +257,11 @@ Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'000000000000000000
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yosys> proc_dlatch
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11.8. Executing PROC_DLATCH pass (convert process syncs to latches).
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13.8. Executing PROC_DLATCH pass (convert process syncs to latches).
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yosys> proc_dff
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11.9. Executing PROC_DFF pass (convert process syncs to FFs).
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13.9. Executing PROC_DFF pass (convert process syncs to FFs).
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Creating register for signal `\fifo.\count' using process `\fifo.$proc$fifo.v:64$24'.
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created $adff cell `$procdff$55' with positive edge clock and positive level reset.
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Creating register for signal `\fifo.\rdata' using process `\fifo.$proc$fifo.v:38$16'.
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@ -269,11 +277,11 @@ Creating register for signal `$paramod\addr_gen\MAX_DATA=s32'0000000000000000000
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yosys> proc_memwr
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11.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
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13.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
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yosys> proc_clean
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11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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13.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Removing empty process `fifo.$proc$fifo.v:0$31'.
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Found and cleaned up 2 empty switches in `\fifo.$proc$fifo.v:64$24'.
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Removing empty process `fifo.$proc$fifo.v:64$24'.
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@ -286,7 +294,7 @@ Cleaned up 5 empty switches.
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yosys> opt_expr -keepdc
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11.12. Executing OPT_EXPR pass (perform const folding).
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13.12. Executing OPT_EXPR pass (perform const folding).
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Optimizing module fifo.
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Optimizing module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.
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@ -294,13 +302,13 @@ yosys> select -set new_cells t:$memrd
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yosys> show -color maroon3 c:fifo_reader -color cornflowerblue @new_cells -notitle -format dot -prefix rdata_proc o:rdata %ci*
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12. Generating Graphviz representation of design.
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14. Generating Graphviz representation of design.
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Writing dot description to `rdata_proc.dot'.
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Dumping selected parts of module fifo to page 1.
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yosys> flatten
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13. Executing FLATTEN pass (flatten design).
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15. Executing FLATTEN pass (flatten design).
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Deleting now unused module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.
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<suppressed ~2 debug messages>
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@ -313,13 +321,13 @@ yosys> select -set new_cells @rdata_path o:rdata %ci3 %d i:* %d
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yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_flat @rdata_path
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14. Generating Graphviz representation of design.
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16. Generating Graphviz representation of design.
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Writing dot description to `rdata_flat.dot'.
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Dumping selected parts of module fifo to page 1.
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yosys> opt_dff
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15. Executing OPT_DFF pass (perform DFF optimizations).
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17. Executing OPT_DFF pass (perform DFF optimizations).
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Adding EN signal on $procdff$55 ($adff) from module fifo (D = $0\count[8:0], Q = \count).
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Adding EN signal on $flatten\fifo_writer.$procdff$60 ($adff) from module fifo (D = $flatten\fifo_writer.$procmux$51_Y, Q = \fifo_writer.addr).
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Adding EN signal on $flatten\fifo_reader.$procdff$60 ($adff) from module fifo (D = $flatten\fifo_reader.$procmux$51_Y, Q = \fifo_reader.addr).
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@ -328,13 +336,13 @@ yosys> select -set new_cells t:$adffe
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yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_adffe o:rdata %ci*
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16. Generating Graphviz representation of design.
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18. Generating Graphviz representation of design.
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Writing dot description to `rdata_adffe.dot'.
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Dumping selected parts of module fifo to page 1.
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yosys> wreduce
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17. Executing WREDUCE pass (reducing word size of cells).
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19. Executing WREDUCE pass (reducing word size of cells).
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Removed top 31 bits (of 32) from port B of cell fifo.$add$fifo.v:68$27 ($add).
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Removed top 23 bits (of 32) from port Y of cell fifo.$add$fifo.v:68$27 ($add).
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Removed top 31 bits (of 32) from port B of cell fifo.$sub$fifo.v:70$30 ($sub).
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@ -353,20 +361,20 @@ yosys> select -set new_cells t:$add %co t:$add %d
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yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_wreduce o:rdata %ci*
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18. Generating Graphviz representation of design.
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20. Generating Graphviz representation of design.
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Writing dot description to `rdata_wreduce.dot'.
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Dumping selected parts of module fifo to page 1.
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yosys> opt_clean
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19. Executing OPT_CLEAN pass (remove unused cells and wires).
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21. Executing OPT_CLEAN pass (remove unused cells and wires).
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Finding unused cells or wires in module \fifo..
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Removed 0 unused cells and 4 unused wires.
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<suppressed ~1 debug messages>
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yosys> memory_dff
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20. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
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22. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
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Checking read port `\data'[0] in module `\fifo': merging output FF to cell.
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Write port 0: non-transparent.
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@ -374,13 +382,13 @@ yosys> select -set new_cells t:$memrd_v2
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yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_memrdv2 o:rdata %ci*
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21. Generating Graphviz representation of design.
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23. Generating Graphviz representation of design.
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Writing dot description to `rdata_memrdv2.dot'.
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Dumping selected parts of module fifo to page 1.
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yosys> alumacc
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22. Executing ALUMACC pass (create $alu and $macc cells).
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24. Executing ALUMACC pass (create $alu and $macc cells).
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Extracting $alu and $macc cells in module fifo:
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creating $macc model for $add$fifo.v:68$27 ($add).
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creating $macc model for $flatten\fifo_reader.$add$fifo.v:20$34 ($add).
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@ -400,13 +408,13 @@ yosys> select -set new_cells t:$alu t:$macc
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yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdata %ci*
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23. Generating Graphviz representation of design.
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25. Generating Graphviz representation of design.
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Writing dot description to `rdata_alumacc.dot'.
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Dumping selected parts of module fifo to page 1.
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yosys> memory_collect
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24. Executing MEMORY_COLLECT pass (generating $mem cells).
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26. Executing MEMORY_COLLECT pass (generating $mem cells).
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yosys> select -set new_cells t:$mem_v2
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@ -414,6 +422,6 @@ yosys> select -set rdata_path @new_cells %ci*:-$mem_v2[WR_DATA,WR_ADDR,WR_EN] @n
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yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_coarse @rdata_path
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25. Generating Graphviz representation of design.
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27. Generating Graphviz representation of design.
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Writing dot description to `rdata_coarse.dot'.
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Dumping selected parts of module fifo to page 1.
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@ -15,6 +15,8 @@ select t:*
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select -list
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select -set new_cells %
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select -clear
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show -format dot -prefix addr_gen_show addr_gen
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show -format dot -prefix new_cells_show -notitle @new_cells
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show -color maroon3 @new_cells -color cornflowerblue p:* -notitle -format dot -prefix addr_gen_hier
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# ========================================================
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@ -247,7 +247,8 @@ Because the design schematic is quite large, we will be showing just the data
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path for the ``rdata`` output. If you would like to see the entire design for
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yourself, you can do so with :doc:`/cmd/show`. Note that the :cmd:ref:`show`
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command only works with a single module, so you may need to call it with
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||||
:yoscrypt:`show fifo`.
|
||||
:yoscrypt:`show fifo`. :ref:`show_intro` section in
|
||||
:doc:`/getting_started/scripting_intro` has more on how to use :cmd:ref:`show`.
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/rdata_proc.*
|
||||
:class: width-helper
|
||||
|
|
|
|||
|
|
@ -43,6 +43,8 @@ design schematic after running it.
|
|||
We briefly touched on :cmd:ref:`select` when it came up in
|
||||
:cmd:ref:`synth_ice40`, but let's look at it more now.
|
||||
|
||||
.. _select_intro:
|
||||
|
||||
Selections intro
|
||||
^^^^^^^^^^^^^^^^
|
||||
|
||||
|
|
@ -70,16 +72,19 @@ cells, regardless of their type. The active selection is now shown as
|
|||
gives us the ``$add`` and ``$eq`` cells, which we want to highlight for the
|
||||
:ref:`addr_gen_hier` image.
|
||||
|
||||
.. _select_new_cells:
|
||||
|
||||
We can assign a name to a selection with :yoscrypt:`select -set`. In our case
|
||||
we are using the name ``new_cells``, and telling it to use the current
|
||||
selection, indicated by the ``%`` symbol. Then we clear the selection so that
|
||||
the following commands can operate on the full design. While we split that out
|
||||
for this document, we could have done the same thing in a single line by calling
|
||||
:yoscrypt:`select -set new_cells addr_gen/t:*`. If we know we only have the one
|
||||
module in our design, we can even skip the `addr_gen/` part. Looking further
|
||||
down :ref:`the fifo.ys code <fifo-ys>` we can see this with :yoscrypt:`select
|
||||
-set new_cells t:$mux t:*dff`. We can also see in that command that selections
|
||||
don't have to be limited to a single statement.
|
||||
selection, indicated by the ``%`` symbol. We can then use this named selection
|
||||
by referring to it as ``@new_cells``, which we will see later. Then we clear
|
||||
the selection so that the following commands can operate on the full design.
|
||||
While we split that out for this document, we could have done the same thing in
|
||||
a single line by calling :yoscrypt:`select -set new_cells addr_gen/t:*`. If we
|
||||
know we only have the one module in our design, we can even skip the `addr_gen/`
|
||||
part. Looking further down :ref:`the fifo.ys code <fifo-ys>` we can see this
|
||||
with :yoscrypt:`select -set new_cells t:$mux t:*dff`. We can also see in that
|
||||
command that selections don't have to be limited to a single statement.
|
||||
|
||||
Many commands also support an optional ``[selection]`` argument which can be
|
||||
used to override the currently selected objects. We could, for example, call
|
||||
|
|
@ -90,53 +95,100 @@ Detailed documentation of the select framework can be found under
|
|||
:doc:`/using_yosys/more_scripting/selections` or in the command reference at
|
||||
:doc:`/cmd/select`.
|
||||
|
||||
.. _show_intro:
|
||||
|
||||
The show command
|
||||
~~~~~~~~~~~~~~~~
|
||||
|
||||
.. TODO:: scripting_intro/show section
|
||||
While the :cmd:ref:`select` command is very useful, sometimes nothing beats
|
||||
being able to see a design for yourself. This is where :cmd:ref:`show` comes
|
||||
in. Note that this document is just an introduction to the :cmd:ref:`show`
|
||||
command, only covering the basics. For more information, including a guide on
|
||||
what the different symbols represent, see :ref:`interactive_show` and the
|
||||
:doc:`/using_yosys/more_scripting/interactive_investigation` page.
|
||||
|
||||
The :cmd:ref:`show` command requires a working installation of `GraphViz`_ and
|
||||
`xdot`_ for generating the actual circuit diagrams. Below is an example of how
|
||||
this command can be used, showing the changes in the generated circuit at
|
||||
different stages of the yosys tool flow.
|
||||
.. figure:: /_images/code_examples/fifo/addr_gen_show.*
|
||||
:class: width-helper
|
||||
:name: addr_gen_show
|
||||
|
||||
Calling :yoscrypt:`show addr_gen` after :cmd:ref:`hierarchy`
|
||||
|
||||
.. note::
|
||||
|
||||
The :cmd:ref:`show` command requires a working installation of `GraphViz`_
|
||||
and `xdot`_ for displaying the actual circuit diagrams.
|
||||
|
||||
.. _GraphViz: http://www.graphviz.org/
|
||||
|
||||
.. _xdot: https://github.com/jrfonseca/xdot.py
|
||||
|
||||
.. literalinclude:: /code_examples/show/example.ys
|
||||
:language: yoscrypt
|
||||
:caption: docs/source/code_examples/show/example.ys
|
||||
This is the first :yoscrypt:`show` command we called in ``fifo.ys``, :ref:`as we
|
||||
saw above <fifo-ys>`. If we look at the log output for this image we see the
|
||||
following:
|
||||
|
||||
.. literalinclude:: /code_examples/show/example.v
|
||||
:language: Verilog
|
||||
:caption: docs/source/code_examples/show/example.v
|
||||
.. literalinclude:: /code_examples/fifo/fifo.out
|
||||
:language: doscon
|
||||
:start-at: -prefix addr_gen_show
|
||||
:end-before: yosys> show
|
||||
|
||||
.. role:: yoscrypt(code)
|
||||
:language: yoscrypt
|
||||
Calling :cmd:ref:`show` with :yoscrypt:`-format dot` tells it we want to output
|
||||
a ``.dot`` file rather than opening it for display. The :yoscrypt:`-prefix
|
||||
addr_gen_show` option indicates we want the file to be called `addr_gen_show.*`.
|
||||
Remember, we do this in ``fifo.ys`` because we need to store the image for
|
||||
displaying in the documentation you're reading. But if you just want to display
|
||||
the images locally you can skip these two options. The ``-format`` option
|
||||
internally calls the ``dot`` command line program from GraphViz to convert to
|
||||
formats other than ``.dot``. Check `GraphViz output docs`_ for more on
|
||||
available formats.
|
||||
|
||||
.. figure:: /_images/code_examples/show/example_first.*
|
||||
.. _GraphViz output docs: https://graphviz.org/docs/outputs/
|
||||
|
||||
.. note::
|
||||
|
||||
If you are using a POSIX based version of Yosys (such as for Mac or Linux),
|
||||
xdot will be opened in the background and Yosys can continue to be used. If
|
||||
it it still open, future calls to :yoscrypt:`show` will use the same xdot
|
||||
instance.
|
||||
|
||||
The ``addr_gen`` at the end tells it we only want the ``addr_gen`` module, just
|
||||
like when we called :yoscrypt:`select -module addr_gen` in :ref:`select_intro`.
|
||||
That last parameter doesn't have to be a module name, it can be any valid
|
||||
selection string. Remember when we :ref:`assigned a name to a
|
||||
selection<select_new_cells>` and called it ``new_cells``? We saw in the
|
||||
:yoscrypt:`select -list` output that it contained two cells, an ``$add`` and an
|
||||
``$eq``. We can call :cmd:ref:`show` on that selection just as easily:
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/new_cells_show.*
|
||||
:class: width-helper
|
||||
|
||||
``example_first`` - shown after :yoscrypt:`read_verilog example.v`
|
||||
:name: new_cells_show
|
||||
|
||||
.. figure:: /_images/code_examples/show/example_second.*
|
||||
Calling :yoscrypt:`show -notitle @new_cells`
|
||||
|
||||
We could have gotten the same output with :yoscrypt:`show -notitle t:$add t:$eq`
|
||||
if we didn't have the named selection. By adding the :yoscrypt:`-notitle` flag
|
||||
there we can also get rid of the ``addr_gen`` title that would have been
|
||||
automatically added. The last two images were both added for this introduction.
|
||||
The next image is the first one we saw in :doc:`/getting_started/example_synth`:
|
||||
showing the full ``addr_gen`` module while also highlighting ``@new_cells`` and
|
||||
the two ``PROC`` blocks. To achieve this highlight, we make use of the
|
||||
:yoscrypt:`-color` option:
|
||||
|
||||
.. figure:: /_images/code_examples/fifo/addr_gen_hier.*
|
||||
:class: width-helper
|
||||
|
||||
``example_second`` - shown after :yoscrypt:`proc`
|
||||
|
||||
.. figure:: /_images/code_examples/show/example_third.*
|
||||
:class: width-helper
|
||||
|
||||
``example_third`` - shown after :yoscrypt:`opt`
|
||||
Calling :yoscrypt:`show -color maroon3 @new_cells -color cornflowerblue p:* -notitle`
|
||||
|
||||
A circuit diagram is generated for the design in its current state. Various
|
||||
options can be used to change the appearance of the circuit diagram, set the
|
||||
name and format for the output file, and so forth. When called without any
|
||||
special options, it saves the circuit diagram in a temporary file and launches
|
||||
``xdot`` to display the diagram. Subsequent calls to show re-use the ``xdot``
|
||||
instance (if still running).
|
||||
As described in the the :cmd:ref:`help` output for :cmd:ref:`show` (or by
|
||||
clicking on the :cmd:ref:`show` link), colors are specified as :yoscrypt:`-color
|
||||
<color> <object>`. Color names for the ``<color>`` portion can be found on the
|
||||
`GraphViz color docs`_. Unlike the final :cmd:ref:`show` parameter which can
|
||||
have be any selection string, the ``<object>`` part must be a single selection
|
||||
expression or named selection. That means while we can use ``@new_cells``, we
|
||||
couldn't use ``t:$eq t:$add``. In general, if a command lists ``[selection]``
|
||||
as its final parameter it can be any selection string. Any selections that are
|
||||
not the final parameter, such as those used in options, must be a single
|
||||
expression instead.
|
||||
|
||||
For more information on the :cmd:ref:`show` command, including a guide on what
|
||||
the different symbols represent, see :ref:`interactive_show` and the
|
||||
:doc:`/using_yosys/more_scripting/interactive_investigation` page.
|
||||
.. _GraphViz color docs: https://graphviz.org/doc/info/colors
|
||||
|
||||
.. seealso:: :ref:`interactive_show` on the
|
||||
:doc:`/using_yosys/more_scripting/interactive_investigation` page.
|
||||
|
|
|
|||
Loading…
Reference in New Issue