yosys

Commit Graph

Author	SHA1	Message	Date
Eddie Hung	79448f9be0	Update doc that "-retime" calls abc with "-dff -D 1"	2019-12-30 13:28:29 -08:00
Miodrag Milanovic	44c3472b9f	FF should be initialized to 0	2019-10-04 13:27:10 +02:00
Miodrag Milanovic	77d557d00b	Add missing latch mapping	2019-10-04 12:58:11 +02:00
Miodrag Milanovic	8badd4d812	better handling of lut and begin/end add	2019-09-18 17:45:07 +02:00
Miodrag Milanovic	3487b95224	Added simulation models for Efinix and Anlogic	2019-09-15 09:37:16 +02:00
Clifford Wolf	4c449caf9b	Fix missing newline at end of file Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-22 18:06:36 +02:00
Miodrag Milanovic	2897fe4d09	Fix formating	2019-08-11 17:05:24 +02:00
Miodrag Milanovic	ead2b52b5a	one bit enable signal	2019-08-11 13:59:39 +02:00
Miodrag Milanovic	aa0c37722a	fix mixing signals on FF mapping	2019-08-11 11:40:15 +02:00
Miodrag Milanovic	853c755a0c	Replaced custom step with setundef	2019-08-11 11:01:46 +02:00
Miodrag Milanovic	e609537e38	Fixed data width	2019-08-11 10:46:48 +02:00
Miodrag Milanovic	8c8100e0df	Adding new pass to fix carry chain	2019-08-11 10:17:49 +02:00
Miodrag Milanovic	b3a91d6508	cleanup	2019-08-11 08:37:56 +02:00
Miodrag Milanovic	d51b135e33	Fix CO	2019-08-09 12:37:10 +02:00
Miodrag Milanovic	8a3329871b	clock for ram trough gbuf	2019-08-04 12:17:55 +02:00
Miodrag Milanovic	cf96f41c6d	Added bram support	2019-08-04 11:46:36 +02:00
Miodrag Milanovic	6e210f26fa	Custom step to add global clock buffers	2019-08-03 14:40:23 +02:00
Miodrag Milanovic	ab98f604fd	Initial EFINIX support	2019-08-03 13:10:44 +02:00

18 Commits