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yosys
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5,747 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

666 Commits

Author SHA1 Message Date
Clifford Wolf 2feee7415d Improved edif backend 2013-08-27 14:22:11 +02:00
Clifford Wolf 39ee561169 More explicit integer output in verilog backend 2013-08-22 20:31:04 +02:00
Clifford Wolf 4f4cb2307f Added correct encoding of identifiers in EDIF backend 2013-08-22 14:30:33 +02:00
Clifford Wolf aba8639a3f Added edif backend (still under construction) 2013-08-22 11:34:55 +02:00
Clifford Wolf af79b4bd98 Fixed generation of newlines in "dump" output 2013-06-10 12:38:02 +02:00
Clifford Wolf 21d9251e52 Added "dump" command (part ilang backend) 2013-06-02 17:53:30 +02:00
Clifford Wolf 7bfc7b61a8 Implemented proper handling of stub placeholder modules 2013-03-28 09:20:10 +01:00
Clifford Wolf 05ae20f260 Added -notypes option to intersynth backend 2013-03-24 12:05:25 +01:00
Clifford Wolf a0fa259d81 Fixed gcc build (intersynth backend) 2013-03-23 19:01:58 +01:00
Clifford Wolf bee57c808a Various improvements in intersynth backend 2013-03-23 12:02:09 +01:00
Clifford Wolf 80aefb3eaa Added intersynth backend 2013-03-23 10:58:14 +01:00
Clifford Wolf 87c7717566 Avoid verilog-2k in verilog backend 2013-03-21 09:51:25 +01:00
Clifford Wolf 11789db206 More support code for $sr cells 2013-03-14 11:15:00 +01:00
Clifford Wolf 441e5fbfca Fixed a gcc compiler warning [-Wparentheses] 2013-03-03 22:45:06 +01:00
Clifford Wolf 7fccad92f7 Added more help messages 2013-03-01 00:36:19 +01:00
Clifford Wolf 7764d0ba1d initial import 2013-01-05 11:13:26 +01:00