riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
1,553 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

39 Commits

Author SHA1 Message Date
Clifford Wolf 19cff41eb4 Changed frontend-api from FILE to std::istream 2014-08-23 15:03:55 +02:00
Clifford Wolf 1bf7a18fec Added module->ports 2014-08-14 16:22:52 +02:00
Clifford Wolf cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf e6d33513a5 Added module->design and cell->module, wire->module pointers 2014-07-31 14:11:39 +02:00
Clifford Wolf 1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf 3c45277ee0 Added wire->upto flag for signals such as "wire [0:7] x;" 2014-07-28 12:12:13 +02:00
Clifford Wolf 6b34215efd Fixed ilang parser for new RTLIL API 2014-07-27 11:56:35 +02:00
Clifford Wolf 946ddff9ce Changed a lot of code to the new RTLIL::Wire constructors 2014-07-26 20:12:50 +02:00
Clifford Wolf 97a59851a6 Added RTLIL::Cell::has(portname) 2014-07-26 16:11:28 +02:00
Clifford Wolf f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf 2bec47a404 Use only module->addCell() and module->remove() to create and delete cells 2014-07-25 17:56:19 +02:00
Clifford Wolf b17d6531c8 Added "make PRETTY=1" 2014-07-24 17:15:01 +02:00
Clifford Wolf ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
Clifford Wolf a8d3a68971 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 2014-07-23 09:49:43 +02:00
Clifford Wolf 7bffde6abd SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only 2014-07-22 20:39:38 +02:00
Clifford Wolf 4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00
Clifford Wolf a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
Clifford Wolf 3b5f4ff39c Fixed ilang parsing of process attributes 2014-07-22 20:39:37 +02:00
Clifford Wolf d6d0e08834 Fixed make rules for ilang parser 2014-07-22 20:39:37 +02:00
Clifford Wolf 4147b55c23 Added "autoidx" statement to ilang file format 2014-07-21 15:15:18 +02:00
Clifford Wolf 7188542155 Fixed clang -Wdeprecated-register warnings 2014-04-20 14:28:23 +02:00
Clifford Wolf a1be4816d6 Replaced depricated %name-prefix= bison directive 2014-04-20 14:22:11 +02:00
Clifford Wolf 620d51d9f7 Bugfix in ilang frontend autoidx recovery 2014-03-07 17:19:14 +01:00
Clifford Wolf 0defc86519 renamed ilang "scope error" to "ilang error" 2014-02-11 19:17:07 +01:00
Clifford Wolf fb186e6299 Improved ilang parser error messages 2014-02-09 15:35:31 +01:00
Clifford Wolf af325bf206 Fixed comment/eol parsing in ilang frontend 2014-02-01 17:28:02 +01:00
Clifford Wolf 8f11eaaca6 Added updating of RTLIL::autoidx to ilang frontend 2014-01-03 17:51:05 +01:00
Clifford Wolf f4b46ed31e Replaced signed_parameters API with CONST_FLAG_SIGNED 2013-12-04 14:24:44 +01:00
Clifford Wolf 0ef22c7609 Added support for signed parameters in ilang 2013-11-24 17:37:27 +01:00
Clifford Wolf f71e27dbf1 Remove auto_wire framework (smarter than the verilog standard) 2013-11-24 17:29:11 +01:00
Clifford Wolf 09471846c5 Major improvements in mem2reg and added "init" sync rules 2013-11-21 13:49:00 +01:00
Clifford Wolf 08ceb3729e Fixed ilang parser: memory width 2013-11-20 19:55:52 +01:00
Clifford Wolf 77726fb5fe Fixed parsing of value-less attributes in ilang 2013-10-23 18:38:31 +02:00
Clifford Wolf 375f83c5ec Fixed memory leak in ilang frontend 2013-05-23 12:55:59 +02:00
Clifford Wolf 8a6b0a3520 Added help messages to ilang and verilog frontends 2013-03-01 08:03:00 +01:00
Clifford Wolf 6543917fb8 added .gitignore files 2013-01-05 11:19:11 +01:00
Clifford Wolf 7764d0ba1d initial import 2013-01-05 11:13:26 +01:00