Clifford Wolf
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6dec0e0b3e
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Added autotest.sh -p option
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2014-01-02 17:52:48 +01:00 |
Clifford Wolf
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ab3f6266ad
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Use "abc -dff" in "make test"
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2013-12-31 21:25:34 +01:00 |
Clifford Wolf
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a582b9d184
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Fixed commented out techmap call in tests/tools/autotest.sh
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2013-12-31 13:51:25 +01:00 |
Clifford Wolf
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1afe6589df
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Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
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2013-11-24 20:44:00 +01:00 |
Clifford Wolf
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1e6836933d
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Added modelsim support to autotest
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2013-11-24 15:10:43 +01:00 |
Clifford Wolf
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288ba9618a
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Moved common techlib files to techlibs/common
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2013-09-15 11:52:57 +02:00 |
Clifford Wolf
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c8763301b4
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Added $div and $mod technology mapping
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2013-08-09 17:09:24 +02:00 |
Clifford Wolf
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00a6c1d9a5
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Major redesign of expr width/sign detecion (verilog/ast frontend)
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2013-07-09 14:31:57 +02:00 |
Clifford Wolf
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ff4a1dd06c
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Improved vcdcd.pl (added -d option)
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2013-05-14 09:41:47 +02:00 |
Clifford Wolf
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be8ecd6d16
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Some improvements in vcdcd.pl
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2013-05-14 08:50:59 +02:00 |
Clifford Wolf
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2d9cbd3b02
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added more .gitignore files (make test)
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2013-01-05 11:35:52 +01:00 |
Clifford Wolf
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7764d0ba1d
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initial import
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2013-01-05 11:13:26 +01:00 |