yosys

Commit Graph

Author	SHA1	Message	Date
Eddie Hung	7b543fdb0c	xilinx: consider DSP48E1.ADREG	2020-03-04 12:04:02 -08:00
Eddie Hung	512596760b	xilinx: cleanup DSP48E1 handling for abc9	2020-03-04 11:31:12 -08:00
Eddie Hung	78d4fff69d	xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v	2020-03-04 11:31:12 -08:00
Eddie Hung	3ea5506f81	abc9_ops: use TimingInfo for -prep_{lut,box} too	2020-02-27 10:17:29 -08:00
Eddie Hung	8408c13405	Update xilinx for ABC9	2020-02-27 10:17:29 -08:00
Eddie Hung	12d70ca8fb	xilinx: improve specify functionality	2020-02-27 10:17:29 -08:00
Eddie Hung	0e7c55e2a7	Auto-generate .box/.lut files from specify blocks	2020-02-27 10:17:29 -08:00
Eddie Hung	f2576c096c	Merge branch 'eddie/abc9_refactor' into eddie/abc9_required	2020-01-27 12:29:28 -08:00
Eddie Hung	da134701cd	Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0	2020-01-22 14:22:03 -08:00
Eddie Hung	b2259a9201	Add abc9_ops -check, -prep_times, -write_box for required times	2020-01-10 11:45:41 -08:00
Eddie Hung	98ee8c14df	Merge remote-tracking branch 'origin/master' into xaig_dff	2020-01-06 15:02:44 -08:00
Eddie Hung	db04161eca	Rework abc9's DSP48E1 model	2020-01-01 17:30:26 -08:00
Eddie Hung	b4663a987b	Fix attributes on $__ABC9_ASYNC[01] whitebox	2019-12-31 11:14:11 -08:00
Eddie Hung	979bf36fb0	Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t	2019-12-19 11:23:41 -08:00
Eddie Hung	af3055fe83	Add blackbox model for $__ABC9_FF_ so that clock partitioning works	2019-11-20 14:30:56 -08:00
Eddie Hung	3879ca1398	Do not require changes to cells_sim.v; try and work out comb model	2019-10-05 22:55:18 -07:00
Eddie Hung	7a45cd5856	Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff	2019-10-04 16:58:55 -07:00
Eddie Hung	aae2b9fd9c	Rename abc_* names/attributes to more precisely be abc9_*	2019-10-04 11:04:10 -07:00

18 Commits