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162 Commits

Author SHA1 Message Date
Clifford Wolf 7815f81c32 Added "synth" command 2014-09-14 16:09:06 +02:00
Clifford Wolf 76f8128123 Fixed autotest for non-basename arguments 2014-09-06 12:10:57 +02:00
Clifford Wolf 01ef34c147 Added tests/various/constmsk_test.ys 2014-09-04 15:07:30 +02:00
Clifford Wolf 88db09255b Added autotest -e (do not use -noexpr on write_verilog) 2014-08-30 18:34:07 +02:00
Clifford Wolf c2df5b9175 Cosmetic changes to FSM tests 2014-08-21 17:40:49 +02:00
Clifford Wolf 28cf48e31f Some improvements in FSM mapping and recoding 2014-08-14 11:22:45 +02:00
Clifford Wolf 1dd8252169 Added test_verific mode to tests/fsm/generate.py 2014-08-12 15:43:30 +02:00
Clifford Wolf cad98bcd89 Added multi-dim memory test (requires iverilog git head) 2014-08-12 10:37:47 +02:00
Clifford Wolf 788bd02f97 Fixed FSM mapping for multiple reset-like signals 2014-08-10 12:04:02 +02:00
Clifford Wolf 2faef89738 Some improvements in fsm_opt and fsm_map for FSM with unreachable states 2014-08-09 14:49:51 +02:00
Clifford Wolf 51aa5544fb Improved FSM tests 2014-08-08 15:08:11 +02:00
Clifford Wolf c07774b0b6 Added FSM test bench 2014-08-08 13:12:18 +02:00
Clifford Wolf 91dd87e60b Improved scope resolution of local regs in Verilog+AST frontend 2014-08-05 12:15:53 +02:00
Clifford Wolf 0129d41efa Fixed AST handling of variables declared inside a functions main block 2014-08-05 08:35:51 +02:00
Clifford Wolf 358bf70a21 Added "wreduce" to some of the standard test benches 2014-08-03 20:22:33 +02:00
Clifford Wolf 5e641acc90 Consolidated hana test benches into fewer files 
for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
    ${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;

..etc..
 2014-08-01 03:57:37 +02:00
Clifford Wolf 03ef9a75c6 Added "test_autotb -n <num_iter>" option 2014-08-01 03:55:51 +02:00
Clifford Wolf 7d98645fe8 Added "make -j{N}" support to "make test" 2014-07-30 19:23:26 +02:00
Clifford Wolf e6df25bf74 Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ 2014-07-29 21:12:50 +02:00
Clifford Wolf 27a872d1e7 Added support for "upto" wires to Verilog front- and back-end 2014-07-28 14:25:03 +02:00
Clifford Wolf c469be883b Improvements in tests/vloghtb 2014-07-28 09:15:40 +02:00
Clifford Wolf 8b0f50792c Added techmap -extern 2014-07-27 21:31:18 +02:00
Clifford Wolf d49dec1f86 Added tests/various/.gitignore 2014-07-26 17:43:41 +02:00
Clifford Wolf b21ebe1859 Added tests/various/submod_extract.ys 2014-07-26 17:22:18 +02:00
Clifford Wolf 027819c7e8 Use "wget -N" in tests/vloghtb/run-test.sh 2014-07-26 14:08:43 +02:00
Clifford Wolf 50f22ff30c Renamed some of the test cases in tests/simple to avoid name collisions 2014-07-25 13:01:45 +02:00
Clifford Wolf 0229d68fc9 Use "opt -fine" in test/vloght/test_mapopt.sh 2014-07-21 21:39:59 +02:00
Clifford Wolf 1241a9fd50 Added "opt_const -fine" and "opt_reduce -fine" 2014-07-21 16:34:16 +02:00
Clifford Wolf 668306d00f Various improvements in test/vloghtb 2014-07-21 14:40:57 +02:00
Clifford Wolf 3cb61d03f8 Wider range of cell types supported in "share" pass 2014-07-21 12:18:29 +02:00
Clifford Wolf 8836943693 Added yet another resource sharing test case 2014-07-20 21:15:01 +02:00
Clifford Wolf e9506bb2da Supercell creation for $div/$mod worked all along, fixed test benches 2014-07-20 18:54:06 +02:00
Clifford Wolf 7a6d578b81 Improved tests/share/generate.py 2014-07-20 17:06:57 +02:00
Clifford Wolf 4af8d84f01 Small fix in tests/vloghtb/run-test.sh 2014-07-20 17:05:20 +02:00
Clifford Wolf 4c38ec1cc8 Added "miter -equiv -flatten" 2014-07-20 15:33:07 +02:00
Clifford Wolf 2e358bd667 Added tests/vloghtb/test_share.sh 2014-07-20 15:33:05 +02:00
Clifford Wolf 6f450d0224 Added tests/share for testing "share" supercell creation 2014-07-20 15:32:59 +02:00
Clifford Wolf 3f9f0c047d Added tests/vloghtb 2014-07-20 02:19:44 +02:00
Clifford Wolf 297a0962ea Added SAT-based write-port sharing to memory_share 2014-07-19 15:33:55 +02:00
Clifford Wolf 26f982ac0b Fixed bug in memory_share feedback-to-en code 2014-07-19 15:32:14 +02:00
Clifford Wolf e441f07d89 Added translation from read-feedback to en-signals in memory_share 2014-07-18 16:46:40 +02:00
Clifford Wolf ddb01df42e Bugfix in tests/memories/run-test.sh 2014-07-18 13:45:25 +02:00
Clifford Wolf 5d9127418b added tests/memories 2014-07-18 13:25:19 +02:00
Clifford Wolf ec3a798194 Also simulate unmapped memories in "make test" 2014-07-17 16:53:52 +02:00
Clifford Wolf 9b183539af Implemented dynamic bit-/part-select for memory writes 2014-07-17 16:49:23 +02:00
Clifford Wolf 5867f6bcdc Added support for bit/part select to mem2reg rewriter 2014-07-17 13:49:32 +02:00
Clifford Wolf 6d69d4aaa8 Added support for constant bit- or part-select for memory writes 2014-07-17 13:13:21 +02:00
Clifford Wolf 73a345294a Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface 2014-07-16 14:08:51 +02:00
Clifford Wolf 964a67ac41 Added note to "make test": use git checkout of iverilog 2014-07-16 10:03:07 +02:00
Clifford Wolf 3b52121d32 now ignore init attributes on non-register wires in sat command 2014-07-05 11:18:38 +02:00