Claire Xenia Wolf
72787f52fc
Fixing old e-mail addresses and deadnames
...
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
gatecat
cae905f551
Blackbox all whiteboxes after synthesis
...
This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 21:07:20 +00:00
Marcelina Kościelnicka
a786091b46
achronix: Use dfflegalize.
2020-07-14 23:12:16 +02:00
whitequark
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
Marcelina Kościelnicka
aee439360b
Add force_downto and force_upto wire attributes.
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Fixes #2058 .
2020-05-19 01:42:40 +02:00
Marcelina Kościelnicka
38a0c30d65
Get rid of dffsr2dff.
...
This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part. Thus, it never
actually does anything and can be safely removed.
2020-04-15 16:22:37 +02:00
Miodrag Milanovic
cd5c177739
Remove executable flag from files
2020-02-15 10:36:44 +01:00
Eddie Hung
79448f9be0
Update doc that "-retime" calls abc with "-dff -D 1"
2019-12-30 13:28:29 -08:00
Eddie Hung
aa6d06c1b5
Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""
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This reverts commit 6008bb7002
.
2019-12-30 13:28:29 -08:00
Larry Doolittle
e2fc18f27b
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
Clifford Wolf
e041ae3c6d
Merge pull request #777 from mmicko/achronix_cell_sim_fix
...
Fix cells_sim.v for Achronix FPGA
2019-01-04 15:18:18 +01:00
Miodrag Milanovic
50ef4561d4
Fix cells_sim.v for Achronix FPGA
2019-01-04 15:15:23 +01:00
Miodrag Milanovic
3b17c9018a
Unify usage of noflatten among architectures
2019-01-04 11:37:25 +01:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
...
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
c60k28
efed2420d6
Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device
2018-03-31 22:48:47 -06:00
Larry Doolittle
efaef82f75
Squelch trailing whitespace, including meta-whitespace
2018-03-11 16:03:41 +01:00
dh73
1fc061d90c
Organizing Speedster file names
2017-11-08 20:23:55 -06:00
dh73
cbaba62401
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
2017-10-01 11:04:17 -05:00