yosys

Commit Graph

Author	SHA1	Message	Date
Marcelina Kościelnicka	8501342fc5	synth_xilinx: Use opt_dff. The main part is converting xilinx_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.	2020-07-30 22:26:09 +02:00
Marcin Kościelnicki	d48950d92d	xilinx: Initial support for LUT4 devices. Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547	2020-02-07 09:03:22 +01:00
Miodrag Milanovic	ccfe1e5909	this one is fine	2020-01-10 15:20:50 +01:00
Miodrag Milanovic	af852a0ea8	Fix tests	2020-01-10 14:48:01 +01:00
Miodrag Milanovic	a82c701668	Make test without iopads	2019-12-28 16:22:24 +01:00
Miodrag Milanovic	509da7ed1a	Revert "Fix xilinx tests, when iopads are default" This reverts commit `477e43d921`.	2019-12-28 16:12:45 +01:00
Miodrag Milanovic	477e43d921	Fix xilinx tests, when iopads are default	2019-12-21 13:18:44 +01:00
Marcin Kościelnicki	a235250403	xilinx: Add xilinx_dffopt pass (#1557 )	2019-12-18 13:43:43 +01:00
Marcin Kościelnicki	aff6ad1ce0	xilinx: Improve flip-flop handling. This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data.	2019-12-18 13:43:43 +01:00
Miodrag Milanovic	3e0ffe05a7	Fixed tests	2019-11-11 15:41:33 +01:00
Miodrag Milanovic	5603595e5c	Share common tests	2019-10-18 12:19:59 +02:00
Miodrag Milanovic	c2ec7ca703	Moved all tests in arch sub directory	2019-10-18 11:06:12 +02:00

12 Commits