7 Commits

Author	SHA1	Message	Date
Clifford Wolf	9ac560f5d3	Add "dffinit -highlow" and fix synth_intel ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-01-09 18:42:19 +01:00
Clifford Wolf	0bc95f1e04	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
Marcus Comstedt	8c2bdef36d	Fix a segfault in dffinit when the value has too few bits ... The code was already trying to add the required number of bits, but fell one short of the mark.	2015-11-08 19:16:56 +01:00
Clifford Wolf	207736b4ee	Import more std:: stuff into Yosys namespace	2015-10-25 19:30:49 +01:00
Clifford Wolf	f43815054e	Properly clean up unused "init" attributes	2015-08-18 13:50:15 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	c52a4cdeed	Added "dffinit", Support for initialized Xilinx DFF	2015-04-04 19:00:15 +02:00