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yosys
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5985 Commits

Author SHA1 Message Date
Eddie Hung 2b104ed6c8 Replace with <internal options> 2019-06-26 17:42:50 -07:00
Eddie Hung cae69a3edd Rework help_mode for synth_xilinx -widemux 2019-06-26 17:41:21 -07:00
Eddie Hung da870e62d9 Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux 2019-06-26 17:34:22 -07:00
Eddie Hung dd4667ef2b Emprically (even if I don't fully understand it) this passes picorv32 tb 2019-06-26 17:33:26 -07:00
Eddie Hung f66be9433f Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux 2019-06-26 17:16:11 -07:00
Eddie Hung d7d5ea6e0c Remove redundant check (done further down) 2019-06-26 17:13:56 -07:00
Eddie Hung 5f807a7a5b Return to upstream synth_xilinx with opt -full and wreduce 2019-06-26 16:25:48 -07:00
Eddie Hung 502054e040 Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux 2019-06-26 16:24:38 -07:00
Eddie Hung 5087d1c2c2 Restore sigmap wrapper 2019-06-26 16:16:44 -07:00
Eddie Hung 90750e43ef Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux 2019-06-26 16:07:18 -07:00
Eddie Hung ca1fac7c47 Add more tests 2019-06-26 16:07:07 -07:00
Eddie Hung 9cba05285b muxcover to be undef-sensitive when computing decoders 2019-06-26 16:06:30 -07:00
Eddie Hung 8ef64a19e7 Revert "Rework muxcover decoder gen if more significant muxes are 1'bx" 
This reverts commit b2b5cf78e2.
 2019-06-26 15:13:25 -07:00
Eddie Hung 812469aaa3 Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux 2019-06-26 14:48:35 -07:00
Eddie Hung 585e6ddc6c Let's not go crazy: use nonzero costs 2019-06-26 14:16:44 -07:00
Eddie Hung b2b5cf78e2 Rework muxcover decoder gen if more significant muxes are 1'bx 2019-06-26 13:50:19 -07:00
Eddie Hung 6d9ba40263 Add tests 2019-06-26 13:49:51 -07:00
Eddie Hung c762be5930 Instead of blocking wreduce on $mux, use -keepdc instead #1132 2019-06-26 11:48:35 -07:00
Eddie Hung 8d8261c71f Do not call opt with -full before muxcover 2019-06-26 11:38:28 -07:00
Eddie Hung 80de03a7a6 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-26 11:24:39 -07:00
Eddie Hung 4d0014d1b1 Cleanup abc_box_id 2019-06-26 11:23:57 -07:00
Eddie Hung 612083a807 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-26 10:33:54 -07:00
Eddie Hung 5e1b8d458b Remove unused var 2019-06-26 10:33:07 -07:00
Eddie Hung 988e6163ab Add _nowide variants of LUT libraries in -nowidelut flows 2019-06-26 10:23:29 -07:00
Eddie Hung 741ebba70a Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-06-26 10:10:16 -07:00
Eddie Hung 86a5fbcde9 Merge branch 'koriakin/xc7nocarrymux' into xaig 2019-06-26 10:09:59 -07:00
Eddie Hung 138989e1a3 Fix spacing 2019-06-26 10:09:18 -07:00
Eddie Hung df3a037489 Merge branch 'koriakin/xc7nocarrymux' into xaig 2019-06-26 10:08:40 -07:00
Eddie Hung cb722e7b58 Oops. Actually use nocarry flag as spotted by @koriakin 2019-06-26 10:06:33 -07:00
Clifford Wolf 0d2b87e3ed
Merge pull request #1137 from mmicko/cell_sim_fix 
Simulation model verilog fix
 2019-06-26 19:06:10 +02:00
Eddie Hung 799b18263f Merge branch 'koriakin/xc7nocarrymux' into xaig 2019-06-26 10:04:01 -07:00
Miodrag Milanovic ea0b6258ab Simulation model verilog fix 2019-06-26 18:34:34 +02:00
Eddie Hung 4ce329aefd synth_ecp5 rename -nomux to -nowidelut, but preserve former 2019-06-26 09:33:48 -07:00
Eddie Hung 7389b043c0 Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriakin/xc7nocarrymux 2019-06-26 09:33:38 -07:00
Eddie Hung 177c26ca35 Rename -minmuxf to -widemux 2019-06-26 09:16:45 -07:00
Eddie Hung 184cfacfb5 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-26 09:15:28 -07:00
Clifford Wolf 0b7d648c6a Improve opt_clean handling of unused public wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 17:54:17 +02:00
Eddie Hung 4f0cb34495
Merge pull request #1136 from YosysHQ/xaig_ice40_wire_del 
abc9: Add wire delays to synth_ice40
 2019-06-26 08:51:11 -07:00
Clifford Wolf 1b49380f6b Improve BTOR2 handling of undriven wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 17:42:00 +02:00
David Shah 0dd850e655 abc9: Add wire delays to synth_ice40 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-26 11:39:44 +01:00
Clifford Wolf f6053b8810 Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 11:09:43 +02:00
Clifford Wolf 8e9ef891fe Do not clean up buffer cells with "keep" attribute, closes #1128 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 11:01:03 +02:00
Clifford Wolf b3c36b4448 Escape scope names starting with dollar sign in smtio.py 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 10:58:39 +02:00
whitequark 3d4102cfa4 Add more ECP5 Diamond flip-flops. 
This includes all I/O registers, and a few more regular FFs where it
was convenient.
 2019-06-26 01:57:29 +00:00
Eddie Hung 1a4092d26a Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-25 10:39:08 -07:00
Eddie Hung 5db96b8aec Missing muxpack.o in Makefile 2019-06-25 10:38:42 -07:00
Eddie Hung fac3528133 Merge remote-tracking branch 'origin/xaig' into xc7mux 2019-06-25 09:36:12 -07:00
Eddie Hung 480a04cb3c Realistic delays for RAM32X1D too 2019-06-25 09:34:28 -07:00
Eddie Hung 6095357390 Add RAM32X1D box info 2019-06-25 09:34:19 -07:00
Eddie Hung 6f36ec8ecf Merge remote-tracking branch 'origin/master' into xaig 2019-06-25 09:33:11 -07:00