8 Commits

Author	SHA1	Message	Date
Clifford Wolf	73e0e13d2f	Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal	2014-07-16 11:38:02 +02:00
Clifford Wolf	fc3b3c4ec3	Added $slice and $concat cell types	2014-02-07 17:44:57 +01:00
Clifford Wolf	a6750b3753	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	2014-02-03 13:01:45 +01:00
Clifford Wolf	1e67099b77	Added $assert cell	2014-01-19 14:03:40 +01:00
Clifford Wolf	fb2bf934dc	Added correct handling of $memwr priority	2014-01-03 00:22:17 +01:00
Clifford Wolf	fe8ec32a1c	Added new cell types to manual	2013-12-28 12:10:32 +01:00
Clifford Wolf	288ba9618a	Moved common techlib files to techlibs/common	2013-09-15 11:52:57 +02:00
Clifford Wolf	61ed6b32d1	Added Yosys Manual	2013-07-20 15:19:12 +02:00