18 Commits

Author	SHA1	Message	Date
Clifford Wolf	f6ff311a1d	Do not rename VHDL entities to "entity(impl)" when they are top modules ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-11-20 12:54:10 +01:00
Clifford Wolf	9260e97aa2	Automatically prune init attributes in verific front-end, fixes #1237 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-07 15:31:49 +02:00
Eddie Hung	3ea54ec400	Fix verific_parameters construction, use attribute to mark top netlists	2019-05-03 20:53:25 +02:00
Eddie Hung	a27b42e975	WIP -chparam support for hierarchy when verific	2019-05-03 20:53:25 +02:00
Clifford Wolf	3d671630e2	Improve src tagging (using names and attrs) of cells and wires in verific front-end ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-12-18 16:01:22 +01:00
Clifford Wolf	5d9d22f66d	Add "verific -L <int>" option ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-09-04 20:06:10 +02:00
Clifford Wolf	5f2bc1ce76	Add automatic verific import in hierarchy command ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-06-20 23:45:01 +02:00
Clifford Wolf	4372cf690d	Add (* gclk *) attribute support ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-06-01 13:25:42 +02:00
Clifford Wolf	4d645f0fce	Fix verific handling of anyconst/anyseq attributes ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-05-24 17:07:06 +02:00
Clifford Wolf	ab8db2c168	Add "verific -autocover" ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-04-06 14:10:57 +02:00
Clifford Wolf	315d5e32bf	Fix handling of unclocked immediate assertions in Verific front-end ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-26 13:04:10 +02:00
Clifford Wolf	a4bbfd2d15	Fix Verific handling of "assert property (..);" in always block ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-07 20:06:02 +01:00
Clifford Wolf	92d5f4db6f	Add "verific -import -V" ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-07 19:40:34 +01:00
Clifford Wolf	480e8e676a	Add proper SVA seq.triggered support ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-04 19:29:26 +01:00
Clifford Wolf	261cf706f4	Add VerificClocking class and refactor Verific DFF handling ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-04 13:48:53 +01:00
Clifford Wolf	9a2a8cd97b	Fixes and improvements in Verific SVA importer ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-03-01 11:40:43 +01:00
Clifford Wolf	15902d495f	Continue refactoring of Verific SVA importer code ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-28 11:45:04 +01:00
Clifford Wolf	5fa2aa2741	Move Verific SVA importer to extra C++ source file ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-18 13:52:49 +01:00