Eddie Hung
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1237a4c116
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Add warning if synth_xilinx -abc9 with family != xc7
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2019-06-27 11:22:49 -07:00 |
Eddie Hung
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469f98b6bd
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Remove unneeded include
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2019-06-27 11:20:40 -07:00 |
Eddie Hung
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6c256b8cda
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Merge origin/master
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2019-06-27 11:20:15 -07:00 |
Eddie Hung
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c226af3f56
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Fix spacing
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2019-06-26 20:03:34 -07:00 |
Eddie Hung
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080a5ca536
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Improve debugging message for comb loops
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2019-06-26 20:02:38 -07:00 |
Eddie Hung
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4de25a1949
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Add WE to ECP5 dist RAM's abc_scc_break too
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2019-06-26 20:02:19 -07:00 |
Eddie Hung
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a7a88109f5
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Update comment on boxes
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2019-06-26 20:00:15 -07:00 |
Eddie Hung
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b7bef15b16
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Add "WE" to dist RAM's abc_scc_break
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2019-06-26 19:58:09 -07:00 |
Eddie Hung
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26efd6f0a9
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Support more than one port in the abc_scc_break attr
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2019-06-26 19:57:54 -07:00 |
Eddie Hung
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1d0be89214
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Add write_xaiger into CHANGELOG
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2019-06-26 19:17:11 -07:00 |
Eddie Hung
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5fa2afc58c
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Merge branch 'koriakin/xc7nocarrymux' into xaig
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2019-06-26 10:47:53 -07:00 |
Eddie Hung
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6db181471e
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Grrr
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2019-06-26 10:47:03 -07:00 |
Eddie Hung
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5e1b8d458b
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Remove unused var
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2019-06-26 10:33:07 -07:00 |
Eddie Hung
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988e6163ab
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Add _nowide variants of LUT libraries in -nowidelut flows
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2019-06-26 10:23:29 -07:00 |
Eddie Hung
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741ebba70a
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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
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2019-06-26 10:10:16 -07:00 |
Eddie Hung
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86a5fbcde9
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Merge branch 'koriakin/xc7nocarrymux' into xaig
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2019-06-26 10:09:59 -07:00 |
Eddie Hung
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138989e1a3
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Fix spacing
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2019-06-26 10:09:18 -07:00 |
Eddie Hung
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df3a037489
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Merge branch 'koriakin/xc7nocarrymux' into xaig
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2019-06-26 10:08:40 -07:00 |
Eddie Hung
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cb722e7b58
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Oops. Actually use nocarry flag as spotted by @koriakin
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2019-06-26 10:06:33 -07:00 |
Eddie Hung
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799b18263f
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Merge branch 'koriakin/xc7nocarrymux' into xaig
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2019-06-26 10:04:01 -07:00 |
Eddie Hung
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4ce329aefd
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synth_ecp5 rename -nomux to -nowidelut, but preserve former
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2019-06-26 09:33:48 -07:00 |
Eddie Hung
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7389b043c0
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Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriakin/xc7nocarrymux
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2019-06-26 09:33:38 -07:00 |
Eddie Hung
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4f0cb34495
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Merge pull request #1136 from YosysHQ/xaig_ice40_wire_del
abc9: Add wire delays to synth_ice40
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2019-06-26 08:51:11 -07:00 |
David Shah
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0dd850e655
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abc9: Add wire delays to synth_ice40
Signed-off-by: David Shah <dave@ds0.me>
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2019-06-26 11:39:44 +01:00 |
Eddie Hung
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5db96b8aec
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Missing muxpack.o in Makefile
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2019-06-25 10:38:42 -07:00 |
Eddie Hung
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480a04cb3c
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Realistic delays for RAM32X1D too
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2019-06-25 09:34:28 -07:00 |
Eddie Hung
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6095357390
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Add RAM32X1D box info
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2019-06-25 09:34:19 -07:00 |
Eddie Hung
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6f36ec8ecf
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Merge remote-tracking branch 'origin/master' into xaig
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2019-06-25 09:33:11 -07:00 |
Eddie Hung
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ab6e8ce0f0
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Add testcase from #335, fixed by #1130
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2019-06-25 08:43:58 -07:00 |
Clifford Wolf
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add2d415fc
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Merge pull request #1130 from YosysHQ/eddie/fix710
memory_dff: walk through more than one mux for computing read enable
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2019-06-25 17:34:44 +02:00 |
Eddie Hung
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42720ef6fe
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Fix spacing
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2019-06-25 08:33:17 -07:00 |
Eddie Hung
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c4e4902098
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Move only one consumer check outside of while loop
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2019-06-25 08:29:55 -07:00 |
Eddie Hung
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58629dc2ce
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Merge pull request #1129 from YosysHQ/eddie/ram32x1d
Add RAM32X1D support
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2019-06-25 08:22:57 -07:00 |
Clifford Wolf
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e754bce047
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Merge pull request #1075 from YosysHQ/eddie/muxpack
Add new "muxpack" command for packing chains of $mux cells
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2019-06-25 17:21:59 +02:00 |
Eddie Hung
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d2fed0a7f1
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nullptr check
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2019-06-25 06:06:32 -07:00 |
Eddie Hung
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2f770b7400
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Use LUT delays for dist RAM delays
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2019-06-24 23:02:53 -07:00 |
Eddie Hung
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a19226c174
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Fix for abc_scc_break is bus
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2019-06-24 22:16:56 -07:00 |
Eddie Hung
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5605002d8a
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More meaningful error message
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2019-06-24 22:12:55 -07:00 |
Eddie Hung
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4fadb471a3
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Re-enable dist RAM boxes for ECP5
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2019-06-24 22:12:50 -07:00 |
Eddie Hung
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a4a7e63d84
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Revert "Re-enable dist RAM boxes for ECP5"
This reverts commit ca0225fcfa .
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2019-06-24 22:10:28 -07:00 |
Eddie Hung
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babadf5938
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Do not use log_id as it strips \\, also fix scc for |wire| > 1
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2019-06-24 22:04:22 -07:00 |
Eddie Hung
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ca0225fcfa
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Re-enable dist RAM boxes for ECP5
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2019-06-24 21:55:54 -07:00 |
Eddie Hung
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152e682bd5
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Add Xilinx dist RAM as comb boxes
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2019-06-24 21:54:01 -07:00 |
Eddie Hung
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49a762ba46
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Fix abc9's scc breaker, also break on abc_scc_break attr
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2019-06-24 21:53:18 -07:00 |
Eddie Hung
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9dca024a30
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Add tests/various/abc9.{v,ys} with SCC test
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2019-06-24 21:52:53 -07:00 |
Eddie Hung
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cec2292b0b
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Merge remote-tracking branch 'origin/master' into xaig
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2019-06-24 20:01:43 -07:00 |
Eddie Hung
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b7deaceadd
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Walk through as many muxes as exist for rd_en
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2019-06-24 18:33:06 -07:00 |
Eddie Hung
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a701a2accf
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Add test
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2019-06-24 18:32:58 -07:00 |
Eddie Hung
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efd04880db
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Add RAM32X1D support
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2019-06-24 16:16:50 -07:00 |
Clifford Wolf
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e32cef4063
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Merge pull request #1124 from mmicko/json_ports
Add upto and offset to JSON ports
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2019-06-24 08:52:12 +02:00 |